SBOA550 October 2022 OPA1671 , OPA2990 , SN74HCS04 , SN74HCS164 , SN74HCS30 , SN74LVC1G00 , SN74LVC1G123 , TLC04 , TLC14 , TS5A9411
Good quality sinusoidal waveforms can be deceptively difficult to generate. Traditional continuous-time circuits such as the Wien bridge oscillator are simple in principle, but require much additional non-linear circuitry for good performance. It is also becoming difficult to source the components (such as incandescent light bulbs and JFETs) to build the old continuous-time designs. Discrete time solutions usually require expensive precision digital-to-analog converters (DAC) and significant digital logic and firmware that can be too burdensome for many applications. This application note discusses how to use simple Medium Scale Integrated (MSI) logic along with resistors and amplifiers to generate waveforms having well-defined frequency and amplitude, while also providing relatively good harmonic distortion performance.
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Good quality sinusoidal waveforms are often required for test and measurement and audio applications, but generating them with accurate frequency, amplitude, and low harmonic distortion is more difficult than can be expected. Sinusoidal generator circuits broadly fall into two classes: continuous-time and discrete-time solutions. Continuous time circuits such as the Wien bridge or phase-shift oscillators are fundamentally simple, but often require challenging non-linear circuitry to stabilize amplitude, are difficult to tune electronically, and have poor frequency stability. Without feedback control of amplitude, total harmonic distortion below about 1% is difficult to achieve, and amplitude stability can still be problematic over temperature and unit-to-unit variation.
Discrete time circuits based on DACs are now common and can also synthesize non-sinusoidal waveforms. Driving these DACs usually requires substantial digital hardware such as programmable gate arrays or processors, along with the firmware to configure the DAC and clock waveform data through it. Depending on the DAC and reconstruction filter chosen, excellent performance can be achieved but at the expense of this complex digital logic.
In 1969, Tony Davies published an IEEE paper1 documenting how to create sinusoids using a discrete-time approach from a Johnson counter3 and weighted resistors summing up to an output similar to a finite impulse response filter. Davies’ analysis is z-domain based; an approach now used for most modern digital signal processing problems. Referring to this earlier work, in 1976 Don Lancaster demonstrated2 an implementation using 4000-series MSI logic for a simple generator having reasonably good results but with the potential for much better performance by further scaling up the circuit.
This approach is tailored specifically for sinusoids and requires only a simple Johnson counter and a symmetric array of weighted resistors (Figure 2-1) to create a stepped-sinusoid output akin to a discrete time DAC-based device. The stepped-sinusoid is easily filtered to remove residual harmonics for the final output, and frequency can be stepped very quickly. This approach solves the problems associated with continuous time circuits but without the need for substantial logic or programmable devices and their related firmware, or DACs. Using modern and economical MSI components such as the HCS logic series from Texas Instruments, sinusoids up through 10’s of MHz can be created. Frequency and amplitude stability are limited only by the precisions of the time base and reference voltage used, and Total Harmonic Distortion (THD) performance can be improved as needed by using a larger shift register or additional harmonic filtering to meet the applicable specifications. This paper re-examines this approach and provides additional guidance on how to choose the resistor network to optimize THD using the standard EIA component values available. Simulation is used to verify results.
Figure 2-1 shows a simplified configuration of a 6-bit Johnson counter and related resistors to form a stepped-sinusoid output. Careful selection of the resistor values maps each state of the Johnson counter onto a point of the cosine function. As the Johnson counter is clocked through the states, a stepped sinusoid appears at the amplifier output. Extending the length of the shift register or using additional harmonic filtering (not shown) improves harmonic distortion performance.
A Johnson counter is a type of ring counter commonly used for state machines or clock division and must be properly reset at power up. Using a common clock, for each clock pulse the bit pattern shifts right with the output of the rightmost flip-flop inverted (or the output used if available) and fed back to the input of the shift register. This counter can be clocked relatively fast since the only propagation delay involved is from CLK to Q or Q, whichever is slower.
Table 2-1 shows the repeating bit pattern of a 6-bit Johnson counter as the counter evolves over 12 clock cycles starting from a reset state. Twelve clock pulses sequence a 6-bit counter through all desired states.
CLK | Q0 | Q1 | Q2 | Q3 | Q4 | Q5 |
---|---|---|---|---|---|---|
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
↑ | 1 | 0 | 0 | 0 | 0 | 0 |
↑ | 1 | 1 | 0 | 0 | 0 | 0 |
↑ | 1 | 1 | 1 | 0 | 0 | 0 |
↑ | 1 | 1 | 1 | 1 | 0 | 0 |
↑ | 1 | 1 | 1 | 1 | 1 | 0 |
↑ | 1 | 1 | 1 | 1 | 1 | 1 |
↑ | 0 | 1 | 1 | 1 | 1 | 1 |
↑ | 0 | 0 | 1 | 1 | 1 | 1 |
↑ | 0 | 0 | 0 | 1 | 1 | 1 |
↑ | 0 | 0 | 0 | 0 | 1 | 1 |
↑ | 0 | 0 | 0 | 0 | 0 | 1 |
↑ | 0 | 0 | 0 | 0 | 0 | 0 |
A counter of length N completes a full count cycle every 2 × N clock edges so the sinusoidal output frequency is determined with Equation 1.
This counter only uses a fraction of the possible states available from the flip-flops. See Appendix B for important details regarding unused flip-flop states and how to avoid them.
Referring back to Figure 2-1, each resistor contributes a weighted current into the virtual ground node at the op amp, summing to I I Note how the resistor values are used in pairs (for an even length register). For symmetry reasons, assume the outputs of the flip-flops are represented by ±1-V logic levels (rather than binary 1 or 0) so each pair of Ri resistors contributes , , or 0 current toward I depending on the state of the counter. For a counter of even length, the ideal normalized resistor values are computed as Equation 2.
For an odd length register (use Equation 3).
The middle resistor is shown in Equation 4.
See Appendix A for derivations of Equation 2 through Equation 4. Table 2-2 summarizes these values for registers up to length 16. Given the standard MSI devices available, of particular interest are register lengths 4, 6, 8, and 16. Any even-length register can also produce quadrature output. For applications requiring three-phase output, register lengths 6, 9, and 12 are useful. Registers of lengths 6 and 12 can produce both three-phase and quadrature output. Notice the parallel combination of all resistors in a given array is 1 Ω.
Length | Ideal , Normalized to 1 Ω | |||||||
---|---|---|---|---|---|---|---|---|
N | R0 | R1 | R2 | R3 | R4 | R5 | R6 | R7 |
1 | 1.000 | |||||||
2 | 2.000 | |||||||
3 | 4.000 | 2.000 | ||||||
4 | 6.828 | 2.828 | ||||||
5 | 10.472 | 4.000 | 3.236 | |||||
6 | 14.928 | 5.464 | 4.000 | |||||
7 | 20.196 | 7.208 | 4.988 | 4.494 | ||||
8 | 26.274 | 9.226 | 6.165 | 5.226 | ||||
9 | 33.163 | 11.518 | 7.518 | 6.128 | 5.759 | |||
10 | 40.863 | 14.081 | 9.040 | 7.174 | 6.472 | |||
11 | 49.374 | 16.915 | 10.730 | 8.353 | 7.323 | 7.027 | ||
12 | 58.695 | 20.020 | 12.585 | 9.657 | 8.293 | 7.727 | ||
13 | 68.827 | 23.396 | 14.604 | 11.084 | 9.369 | 8.545 | 8.296 | |
14 | 79.770 | 27.042 | 16.787 | 12.631 | 10.548 | 9.462 | 8.988 | |
15 | 91.523 | 30.959 | 19.134 | 14.297 | 11.825 | 10.472 | 9.780 | 9.567 |
16 | 104.087 | 35.146 | 21.643 | 16.082 | 13.198 | 11.568 | 10.661 | 10.252 |