LP38798 800-mA Ultra-Low-Noise, High-PSRR LDO
- SNOSCT6F March 2013 – January 2017 LP38798
  
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DATA SHEET

LP38798 800-mA Ultra-Low-Noise, High-PSRR LDO

1 Features

Wide Operating Input Voltage Range:
3 V to 20 V
Ultra-Low Output Noise: 5 µV_RMS
(10 Hz to 100 kHz)
High PSRR: 90 dB at 10 kHz, 60 dB at 100 kHz
±1% Output Voltage Initial Accuracy (T_J = 25°C)
Very Low Dropout: 200 mV (Typical) at 800 mA
Stable with Ceramic or Tantalum Output Capacitors
Excellent Line and Load Transient Response
Current Limit and Overtemperature Protection
Create a Custom Design Using the LP38798 With the WEBENCH® Power Designer

2 Applications

RF Power Supplies: PLLs, VCOs, Mixers, LNAs
Telecom Infrastructure
Wireless Infrastructure
Very Low-Noise Instrumentation
Precision Power Supplies
High-Speed, High-Precision Data Converters

3 Description

The LP38798-ADJ is a high-performance, low-noise LDO that can supply up to 800 mA output current. Designed to meet the requirements of sensitive RF/Analog circuitry, the LP38798-ADJ implements a novel linear topology on an advanced CMOS process to deliver ultra-low output noise and high PSRR at switching power supply frequencies. The LP38798SD-ADJ is stable with both ceramic and tantalum output capacitors and requires a minimum output capacitance of only 1 µF for stability.

The LP38798-ADJ can operate over a wide input voltage range (3 V to 20 V) making it well suited for many post-regulation applications.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LP38798	WSON (12)	4.00 mm × 4.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

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Simplified Schematic

4 Revision History

Changes from E Revision (August 2016) to F Revision

Created Rev F toonly add WEBENCH links to data sheetGo

Changes from D Revision (June 2016) to E Revision

Changed title of data sheet and updated list of Applications Go
Changed first wording of first sentence of Description Go

Changes from C Revision (June2016) to D Revision

Added 1.2 V row to Table 1 Go
Changed "Value for R2 = 12.9 kΩ and 100 kΩ" to "R2 = 12.9 kΩ minimum to 100 kΩ maximum"Go
Changed "value of 13.3 kΩ" to "value of 15 kΩ for R2"Go
Changed "for R1 is" to "needed for R1 to provide an output voltage of 5 V is"Go

Changes from B Revision (December 2014) to C Revision

Changed "linear regulator" to "LDO" on page 1; add top nav icon for reference designGo
Changed Handling Ratings table to ESD Ratings table; move storage temperature to Abs Max table Go
Added links for Community Resources Go

Changes from A Revision (May 2013) to B Revision

Added Device Information and Handling Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; updated Thermal Information; moved some curves to Application Curves sectionGo

5 Pin Configuration and Functions

DNT Package

12-Pin WSON

Top View

Connect WSON DAP to GND at Pins 6 and 7.

Pin Functions

PIN		I/O	DESCRIPTION
NUMBER	NAME	I/O	DESCRIPTION
1, 2	IN	I	Device unregulated input voltage pins. Connect pins together at the package.
3	IN(CP)	I	Charge pump input voltage pin. Connect directly to pins 1 and 2 at the package.
4	CP	O	Charge pump output. See Charge Pump section in Application and Implementation for more information.
5	EN	I	Enable pin. This pin has an internal pullup to turn the LDO output on by default. A logic low level turns the LDO output Off, and reduce the operating current of the device. See Enable Input Operation section in Application and Implementation for more information.
6	GND(CP)	—	Device charge pump ground pin.
7	GND	—	Device analog ground pin.
8	FB	i	Feedback pin for programming the output voltage.
9	SET	I/O	Reference voltage output, and noise filter input. A feedback resistor divider network from this pin to FB and GND will set the output voltage of the device.
10	OUT(FB)	I	OUT buffer feedback input pin. Connect directly to pins 11 and 12 at the package.
11, 12	OUT	O	Device regulated output voltage pins. Connect pins together at the package.
Exposed Pad	DAP	—	The exposed die attach pad on the bottom of the package must be connected to a copper thermal pad on the PCB at ground potential. Connect to ground potential or leave floating. Do not connect to any potential other than the same ground potential seen at device pins 6 (GND(CP)) and 7 (GND). See Thermal Considerations section in Layout for more information.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
V_IN, V_IN(CP)	–0.3	22	V
V_OUT, V_OUT(FB)	–0.3	V_IN + 0.3	V
V_SET	–0.3	V_IN + 0.3	V
V_FB	–0.3	V_IN + 0.3	V
V_EN	–0.3	6	V
Power dissipation⁽²⁾		Internally Limited
I_OUT (Survival)		Internally Limited
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The value of R_θJAfor the WSON package is dependent on PCB copper area, copper thickness, the number of copper layers in the PCB, and the number of thermal vias under the exposed thermal pad (DAP). Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator may go into thermal shutdown. See Thermal Considerations.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

	MIN	MAX	UNIT
Input voltage, V_IN	3	20	V
Output voltage, V_OUT	1.2	(V_IN – V_DO)	V
Enable voltage, V_EN	0	5	V
Junction temperature, T_J	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP38798	UNIT
		DNT (WSON)
		12 PINS
R_θJA	Junction-to-ambient thermal resistance	35.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.4	°C/W
R_θJB	Junction-to-board thermal resistance	12.6	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	12.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.6	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

6.5 Electrical Characteristics

Unless otherwise stated the following conditions apply: V_IN = 5.5 V, V_SET = 5 V, C_CP = 10 nF X7R, C_IN = 10 μF, 50-mΩ tantalum, C_OUT = 10 μF X7R MLCC, I_OUT = 10 mA, and T_J = –40°C to +125°C.

PARAMETER		TEST CONDITIONS	MIN⁽¹⁾	TYP⁽²⁾	MAX⁽¹⁾	UNIT
V_FB	Feedback voltage	V_IN = 5.5 V T_J = 25°C	1.188	1.2	1.212	V
V_FB	Feedback voltage	5.5 V ≤ V_IN ≤ 20 V	1.176	1.2	1.224	V
V_OS	V_OUT – V_SET		0	3.5	16	mV
I_FB	Feedback pin current	V_FB = 1.2 V		0	1	µA
I_SET	SET pin internal current sink	V_IN = 3 V, V_SET = 2.5 V		46		μA
		V_IN = 5.5 V, V_SET = 5 V	25.2	52	67.8
		V_IN = 12.5 V, V_SET = 12 V		71
ΔV_OUT / ΔV_IN	Line regulation⁽³⁾	5.5 V ≤ V_IN ≤ 20 V I_OUT = 10 mA		0.005		%/V
ΔV_OUT / ΔI_OUT	Load regulation⁽⁴⁾	V_IN = 5.5 V 10 mA ≤ I_OUT ≤ 800 mA		–0.2		%/A
V_DO	Dropout voltage⁽⁵⁾	I_OUT = 800 mA		200	420	mV
UVLO	Undervoltage lock-out	V_IN Rising until output is On	2.47	2.65	2.83	V
ΔUVLO	UVLO hysteresis	V_IN Falling from > UVLO threshold until output is Off		180		mV
I_GND	Ground pin current⁽⁶⁾	I_OUT = 800 mA		1.4	2.25	mA
I_GND	Ground pin current⁽⁶⁾	V_IN = 20 V, I_OUT = 800 mA		1.6	2.51	mA
I_Q	Ground pin current, quiescent⁽⁶⁾	I_OUT = 0 mA		1.4	2.1	mA
I_Q	Ground pin current, quiescent⁽⁶⁾	V_IN = 20 V, I_OUT = 0 mA		1.5	2.2	mA
I_SD	Ground pin current, shutdown⁽⁶⁾	V_EN = 0 V		9	20	µA
I_SD	Ground pin current, shutdown⁽⁶⁾	V_IN = 20 V, V_EN = 0 V		12	40	µA
I_SC	Short-circuit current	R_LOAD = 0 Ω	850	1200	1600	mA
ΔV_CP	V_CP – V_IN			2.8		V
ΔV_CP	V_CP – V_IN	V_IN = 20 V		2.3		V
t_START	Start-up time	From V_EN > V_EN(ON) to V_OUT ≥ 98% of V_OUT(NOM)		155	300	µs
PSRR	Power Supply Rejection Ratio	V_OUT = 1.2 V, f = 10 kHz		110		dB
		V_OUT = 5 V, f = 10 kHz		90
		V_OUT = 1.2 V, f = 100 kHz		90
		V_OUT = 5 V, f = 100 kHz		60
		V_OUT = 1.2 V, f = 1 MHz		70
		V_OUT = 5 V, f = 1 MHz		60
e_N	Output noise voltage (RMS)	V_IN = 3 V, V_OUT = 1.2 V C_OUT = 1 µF X7R BW = 10 Hz to 100 kHz		4.96		µV_(RMS)
		V_IN = 3 V, V_OUT = 1.2 V BW = 10 Hz to 100 kHz		5.21
		V_IN = 3 V, V_OUT = 1.2 V BW = 10 Hz to 10 MHz		11.53
		V_IN = 6 V, V_OUT = 5 V C_OUT = 1 µF X7R BW = 10 Hz to 100 kHz		5.38
		V_IN = 6 V, V_OUT = 5 V BW = 10 Hz to 100 kHz		5.43
		V_IN = 6 V, V_OUT = 5 V BW = 10 Hz to 10 MHz		11.58
ENABLE INPUT
V_EN(ON)	Enable ON threshold voltage	V_EN rising from 500 mV until Output is ON	1.14	1.24	1.34	V
ΔV_EN	Enable threshold voltage hysteresis	V_EN falling from V_EN(ON)		110		mV
I_EN(IL)	EN pin pullup current	V_EN = 500 mV		2	3	µA
I_EN(IH)	EN pin pullup current	V_EN = 2 V		2	3	µA
V_EN(CLAMP)	Enable pin clamp voltage	EN pin = Open		5		V
THERMAL SHUTDOWN
T_SD	Thermal shutdown	Junction temperature (T_J) rising		170		°C
ΔT_SD	Thermal shutdown hysteresis	Junction temperature (T_J) falling from T_SD		12		°C

(1) Minimum and maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature (T_J ) range of –40°C to 125°C, unless otherwise stated.

(2) Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only.

(3) Line Regulation: % change in V_OUT(NOM) for every 1V change in V_IN= (( ΔV_OUT / V_OUT(NOM)) / ΔV_IN ) × 100%

(4) Load Regulation: % change in V_OUT(NOM) for every 1A change in I_OUT = (( ΔV_OUT / V_OUT(NOM) ) / ΔI_OUT ) × 100%

(5) Dropout voltage (V_DO) is defined as the differential voltage measured between V_OUT and V_IN when V_IN, falling from V_IN = V_OUT + 1 V, causes V_OUT to drop 2% below the value measured with V_IN = V_OUT + 1 V. Dropout voltage specification does not apply when the programmed output voltage is below the Minimum Operating Input Voltage.

(6) Ground pin current is the sum of the current in both GND pins (pin 4 and pin 5) only, and does not include current from the SET pin.

6.6 Typical Characteristics

Unless otherwise specified: V_IN = 5.5 V, V_OUT = 5 V, I_OUT = 10 mA, C_OUT = 10 µF MLCC 16 V X7R, and T_J = 25°C.

Figure 1. PSRR

Figure 3. Noise Density

Figure 5. PSRR

Figure 7. PSRR

Figure 9. PSRR

Figure 11. UVLO Thresholds vs T_J

Figure 13. Enable Thresholds vs V_IN

Figure 15. Start-Up Time

Figure 17. V_OUT vs Rising V_IN

Figure 19. IN Pin Current vs V_IN

Figure 21. Enable Pin Pull-Up Current vs V_IN

Figure 23. Dropout Voltage vs Output Current

Figure 25. Load Regulation vs T_J

Figure 27. Current Limit, I_SC vs T_J

Figure 29. Line Transient

Figure 31. Line Transient

Figure 33. Line Transient

Figure 35. Load Transient

Figure 37. Load Transient

Figure 39. Load Transient

Figure 2. PSRR

Figure 4. Noise Density

Figure 6. PSRR

Figure 8. PSRR

Figure 10. PSRR

Figure 12. Enable Thresholds vs T_J

Figure 14. Start-Up Time

Figure 16. Start-Up Time

Figure 18. V_FB Variation vs T_J

Figure 20. V_EN(CLAMP) vs V_IN

Figure 22. Dropout Voltage vs Output Current

Figure 24. V_OUT Variation vs T_J

Figure 26. Line Regulation vs T_J

Figure 28. Line Transient

Figure 30. Line Transient

Figure 32. Line Transient

Figure 34. Load Transient

Figure 36. Load Transient

Figure 38. Load Transient

7 Detailed Description

7.1 Overview

The LP38798 is a positive voltage (20 V), ultra-low-noise (5 µV_RMS), low-dropout (LDO) regulator capable of supplying a well-regulated, low-noise voltage to an 800-mA load. The LP38798 uses an advanced design with a CMOS process to deliver ultra low output noise and high PSRR at switching power supply (SMPS) frequencies.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Noise Filter

Any noise at LP38798 SET pin is reduced by an internal passive, first order low-pass RC filter before it is passed to the output buffer stage. The low-pass filter has a –3-dB cut-off frequency of approximately 0.08 Hz.

To keep the low-pass filter from interfering with the output voltage rise time at start-up, a voltage comparator keeps the filter in a fast-charge mode while the output voltage (V_OUT) is less than 99.5% of the SET pin voltage (V_SET) . When the rising V_OUT is within 0.5% of V_SET the fast-charge mode ends, and V_OUT will rise the final 0.5% based on the RC time constant (τ = 2s) of the filter.

Should V_OUT be more than 2% above the V_SET voltage, a voltage comparator will put the filter into the fast-charge mode to allow the filter to discharge and V_OUT to fall a value closer to V_SET. When the falling V_OUT is within 2% of V_SET the fast-charge mode ends, and V_OUT will fall the final 2% based on the RC time constant (τ = 2s) of the filter.

If the input voltage has an extended rise time, the output voltage may exhibit a stair-case waveform as the fast-charge mode is activated and de-activated as V_SET rises with V_IN, and V_OUT follows. Once the V_IN has risen above the programmed V_SET voltage, and V_OUT is within 0.5% of V_SET, the stair-case behavior will end.

7.3.2 Enable Input Operation

The Enable pin (EN) is pulled high internally by a 2 μA (typical) current source from the IN pin, and internally clamped at 5 V (typical) by a zener. Pulling the EN pin low, by sinking the I_EN current to ground, will turn the output off.

If the EN function is not needed the EN pin should be left open (floating). Do not connect the EN pin directly to V_IN if there is any possibility that V_IN might exceed 5.5 V (that is, EN pin AbsMax). If external pullup is required, the external current into the EN pin should be limited to no more than 10 μA.

Equation 1. R_PULL-UP > (V_PULL-UP – 5 V) / 10 μA )

7.3.3 Undervoltage Lockout (UVLO)

The LP38798 incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the LP38798 disabled while a rising V_IN is less than 2.65 V (typical). The rising UVLO threshold is approximately 350 mV below the recommended minimum operating V_IN of 3 V.

7.3.4 Output Current Limiting

The LP38798 incorporates active output current limiting. The threshold for the output current limiting is set well above the ensured output operating current such that it does not interfere with normal operation.

Note that output current limiting is provided as a safety feature and is outside the recommended operating conditions. Operation at the current limit is not recommended as the device junction temperature (T_J) will rise rapidly and operation will likely cross into thermal shutdown behavior .

7.3.5 Thermal Shutdown

The LP38798 includes thermal protection that will shut-off the output current when activated by excessive device dissipation. Thermal shutdown (T_SD) will occur when the junction temperature has risen to 170°C. The junction temperature must fall typically 12°C from the shutdown temperature for the output current to be restored. Junction temperature is calculated from the formula in Equation 2:

Equation 2. T_J = (T_A+ (P_D × R_θJA))

Where the power being dissipated, P_D, is defined as:

Equation 3. P_D = ((V_IN – V_OUT) × I_OUT)

NOTE

Thermal shutdown is provided as a safety feature and is outside the specified Operating Ratings temperature range. Operation with a junction temperature (T_J) above 125°C is not recommended as the device behavior is not specified.

7.4 Device Functional Modes

The LP38798 has two functional modes:

Enabled: When the EN pin voltage is above the V_EN(ON) threshold, and V_IN is above the UVLO threshold, the device is enabled.
Disabled: When the EN pin voltage is below the (V_EN(ON) + ΔV_EN) threshold, or V_IN is below the UVLO threshold, the device is disabled.

7.5 Programming

7.5.1 Programming the Output Voltage

Current sourced from the SET pin, through R1 and R2, must be kept to less than 100 µA. The minimum allowed value for R2 is 12.9 kΩ.

Equation 4. I_SET = V_FB / R2

Equation 5. R2_MIN = V_FB(MAX) / 100 μA

Equation 6. R2_MIN = 12.9 kΩ;

The values for R1 and R2 may be adjusted as needed to achieve the desired output voltage as long as the value for R2 is no less than 12.9 kΩ. The maximum recommended value for R2 is 100 kΩ.

Equation 7 is used to determine the output voltage:

Equation 7. V_OUT = (V_FB × (1 + (R1 / R2 ))) + V_OS

Alternately, Equation 8 can be used to determine the appropriate R1 value for a given R2 value:

Equation 8. R1 = R2 × (((V_OUT) / V_FB) – 1)

Table 1 suggests some ±1% values for R1 and R2 for a range of output voltages using the typical V_FB value of 1.200V. This is not a definitive list, as other combinations exist that will provide similar, possibly better, performance.

Table 1. Typical R1 and R2 Values for Assorted Output Voltages

TARGET V_OUT	R1	R2	TYPICAL V_OUT
1.2 V	0 Ω	15 kΩ	1.2 V
1.5 V	4.22 kΩ	16.9 kΩ	1.5 V
1.8 V	10.5 kΩ	21 kΩ	1.8 V
2 V	10 kΩ	15 kΩ	2 V
2.5 V	16.2 kΩ	15.0 kΩ	2.496 V
3 V	21 kΩ	14 kΩ	3 V
3.3 V	23.2 kΩ	13.3 kΩ	3.293 V
5 V	47.5 kΩ	15 kΩ	5 V

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP38798 is a high-performance linear regulator capable of supplying a well-regulated, low-noise voltage into an 800-mA load. The LP38798 can operate over a wide input voltage range (3 V to 20 V) making it well suited for many post-regulation applications.

8.2 Typical Application: V_OUT= 5 V

Figure 40. Typical Application, V_OUT= 5 V

8.2.1 Design Requirements

DESIGN PARAMETER	EXAMPLE VALUE
Input voltage	5.5 V, ±10%
Output voltage	5. V, ±3.5%
Output current	500 mA

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LP39798 device with the WEBENCH® Power Designer.

Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Input Capacitor Recommendations

The LP38798 is designed and characterized for operation with a ceramic capacitor of 1 µF, or greater, at the input. Note especially that the input capacitances must be located as near as practical to the IN pins

The minimum recommended input capacitance is 1 µF, ceramic or tantalum. However, if the LP38798 is operating in conditions where input ripple, fast changes in the input voltage, or large changes in the load current demand are expected, a minimum input capacitance of 10 µF is strongly recommended

Ceramic capacitor tolerance and variations due temperature and applied voltage must be considered when selecting a capacitor to assure the minimum input capacitance requirement is met over the intended operating range.

The input capacitor must be located as close as physically possible to the input pin and returned to a clean analog ground. Any good quality tantalum capacitor may be used, while a ceramic capacitor should be X5R or X7R rated with appropriate adjustments due to the loss of capacitance value from the applied DC voltage.

Attention must be given to the input capacitance value to minimize transient input voltage droop during load current steps at the OUT pin. Larger input capacitor values are necessary for good transient load response, and have no detrimental influence on the stability of the device. Note, however, that using large value ceramic input capacitances can also cause unwanted ringing at the output if the input capacitor, in combination with the trace inductance, creates a high-Q peaking effect during transients. Short, well-designed interconnect leads to the up-stream supply minimize this effect without adding damping. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred milli-ohms of ESR, in parallel with the ceramic input capacitor.

8.2.2.3 Output Capacitor Recommendations

The LP38798 requires an output capacitance of at least 1 µF, ceramic or tantalum; however, a minimum output capacitance of 10 µF is strongly recommended if fast load transient conditions are expected. While the LP38798 is designed to work with Ceramic output capacitors, the output capacitor can be Ceramic, Tantalum, or a combination. The total output capacitance must be sized appropriately to handle any fast load current steps. Capacitance type, tolerance, ESR, as well as temperature and voltage characteristics, must be considered when selecting an output capacitor for the application.

Note especially that the output capacitances must be located as near as practical to the OUT pins.

Even though the LP38798 is stable with an output capacitance of 1 µF to 10 µF, a single output capacitor will generally not be able to provide the best PSRR performance across a wide frequency range. Multiple parallel capacitors, each with a different self-resonance frequency will provide better performance over a wider frequency range.

The LP38798 is characterized with a ceramic capacitor of 10 µF, or greater, at the output. Noise performance is characterized using a single output capacitor of 10 µF ±10%, 16V, X7R, 1206.

8.2.2.4 Charge Pump

The charge pump is running when both the input voltage is above the UVLO threshold (2.65 V typical) and the EN pin voltage is above the V_EN(ON) threshold (1.24 V typical). The typical charge pump operating frequency is 3.5 MHz.

A low leakage 10 nF X7R storage capacitor is required between the CP pin and ground to store the energy required for gate drive of the internal NMOS pass device. Larger values of capacitance may slow start-up times, while smaller capacitance values may result in degraded dynamic performance.

Do not make any other connection to the CP pin. Loading this pin in any manner degrades regulator performance. No external biasing may be applied to, or derived from, this pin, as permanent damage to the internal charge pump circuitry may occur.

8.2.2.5 Setting the Output Voltage

The output voltage is buffered from the SET pin. The output voltage is defined as:

Equation 9. V_OUT= V_SET = (V_FB × (1 + (R1 / R2))

where

V_FB = 1.2 V (typical)
R2 = 12.9 kΩ minimum to 100 kΩ maximum

Selecting a standard 1% resistor value of 15 kΩ for R2, the resistor value needed for R1 to provide an output voltage of 5V is calculated from:

Equation 10. R1 = R2 × (( V_OUT / V_FB) – 1 )

Equation 11. R1 = 15 kΩ × ((5 V / 1.2 V) – 1)

Equation 12. R1 = 47.5 kΩ

8.2.2.6 Device Dissipation

Device power dissipation is defined as:

Equation 13. P_D = ((V_IN – V_OUT) × I_OUT)

Equation 14. P_D = ((5.5 V - 5 V) × 0.5 A)

Equation 15. P_D = 250 mW

Given 250 mW of device power dissipation, a maximum operating junction temperature (T_J) of 125°C, and presuming a R_θJA of 35.4°C/W, the maximum ambient temperature (T_A) is defined as:

Equation 16. T_A(MAX) = T_J(MAX) – (P_D × R_θJA)

Equation 17. T_A(MAX) = (125°C – (0.25 W × 35.4°C/W))

Equation 18. T_A(MAX) = 116°C

8.2.3 Application Curve

Figure 41. Start-Up Time

9 Power Supply Recommendations

The LP38798 device is designed to operate from an input voltage supply range of 3 V to 20 V. The input supply must be able to supply enough current to keep the input voltage from drooping during load transients and high load current. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.