The LP38798-ADJ is a high-performance, low-noise LDO that can supply up to 800 mA output current. Designed to meet the requirements of sensitive RF/Analog circuitry, the LP38798-ADJ implements a novel linear topology on an advanced CMOS process to deliver ultra-low output noise and high PSRR at switching power supply frequencies. The LP38798SD-ADJ is stable with both ceramic and tantalum output capacitors and requires a minimum output capacitance of only 1 µF for stability.
The LP38798-ADJ can operate over a wide input voltage range (3 V to 20 V) making it well suited for many post-regulation applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LP38798 | WSON (12) | 4.00 mm × 4.00 mm |
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Changes from E Revision (August 2016) to F Revision
Changes from D Revision (June 2016) to E Revision
Changes from C Revision (June2016) to D Revision
Changes from B Revision (December 2014) to C Revision
Changes from A Revision (May 2013) to B Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NUMBER | NAME | ||
1, 2 | IN | I | Device unregulated input voltage pins. Connect pins together at the package. |
3 | IN(CP) | I | Charge pump input voltage pin. Connect directly to pins 1 and 2 at the package. |
4 | CP | O | Charge pump output. See Charge Pump section in Application and Implementation for more information. |
5 | EN | I | Enable pin. This pin has an internal pullup to turn the LDO output on by default. A logic low level turns the LDO output Off, and reduce the operating current of the device. See Enable Input Operation section in Application and Implementation for more information. |
6 | GND(CP) | — | Device charge pump ground pin. |
7 | GND | — | Device analog ground pin. |
8 | FB | i | Feedback pin for programming the output voltage. |
9 | SET | I/O | Reference voltage output, and noise filter input. A feedback resistor divider network from this pin to FB and GND will set the output voltage of the device. |
10 | OUT(FB) | I | OUT buffer feedback input pin. Connect directly to pins 11 and 12 at the package. |
11, 12 | OUT | O | Device regulated output voltage pins. Connect pins together at the package. |
Exposed Pad | DAP | — | The exposed die attach pad on the bottom of the package must be connected to a copper thermal pad on the PCB at ground potential. Connect to ground potential or leave floating. Do not connect to any potential other than the same ground potential seen at device pins 6 (GND(CP)) and 7 (GND). See Thermal Considerations section in Layout for more information. |
MIN | MAX | UNIT | |
---|---|---|---|
VIN, VIN(CP) | –0.3 | 22 | V |
VOUT, VOUT(FB) | –0.3 | VIN + 0.3 | V |
VSET | –0.3 | VIN + 0.3 | V |
VFB | –0.3 | VIN + 0.3 | V |
VEN | –0.3 | 6 | V |
Power dissipation(2) | Internally Limited | ||
IOUT (Survival) | Internally Limited | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±250 |
MIN | MAX | UNIT | |
---|---|---|---|
Input voltage, VIN | 3 | 20 | V |
Output voltage, VOUT | 1.2 | (VIN – VDO) | V |
Enable voltage, VEN | 0 | 5 | V |
Junction temperature, TJ | –40 | 125 | °C |
THERMAL METRIC(1) | LP38798 | UNIT | |
---|---|---|---|
DNT (WSON) | |||
12 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 35.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 29.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 12.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 12.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.6 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(1) | TYP(2) | MAX(1) | UNIT | |
---|---|---|---|---|---|---|
VFB | Feedback voltage | VIN = 5.5 V TJ = 25°C |
1.188 | 1.2 | 1.212 | V |
5.5 V ≤ VIN ≤ 20 V | 1.176 | 1.2 | 1.224 | |||
VOS | VOUT – VSET | 0 | 3.5 | 16 | mV | |
IFB | Feedback pin current | VFB = 1.2 V | 0 | 1 | µA | |
ISET | SET pin internal current sink | VIN = 3 V, VSET = 2.5 V | 46 | μA | ||
VIN = 5.5 V, VSET = 5 V | 25.2 | 52 | 67.8 | |||
VIN = 12.5 V, VSET = 12 V | 71 | |||||
ΔVOUT / ΔVIN | Line regulation(3) | 5.5 V ≤ VIN ≤ 20 V IOUT = 10 mA |
0.005 | %/V | ||
ΔVOUT / ΔIOUT | Load regulation(4) | VIN = 5.5 V 10 mA ≤ IOUT ≤ 800 mA |
–0.2 | %/A | ||
VDO | Dropout voltage(5) | IOUT = 800 mA | 200 | 420 | mV | |
UVLO | Undervoltage lock-out | VIN Rising until output is On | 2.47 | 2.65 | 2.83 | V |
ΔUVLO | UVLO hysteresis | VIN Falling from > UVLO threshold until output is Off | 180 | mV | ||
IGND | Ground pin current(6) | IOUT = 800 mA | 1.4 | 2.25 | mA | |
VIN = 20 V, IOUT = 800 mA | 1.6 | 2.51 | ||||
IQ | Ground pin current, quiescent(6) | IOUT = 0 mA | 1.4 | 2.1 | mA | |
VIN = 20 V, IOUT = 0 mA | 1.5 | 2.2 | ||||
ISD | Ground pin current, shutdown(6) | VEN = 0 V | 9 | 20 | µA | |
VIN = 20 V, VEN = 0 V | 12 | 40 | ||||
ISC | Short-circuit current | RLOAD = 0 Ω | 850 | 1200 | 1600 | mA |
ΔVCP | VCP – VIN | 2.8 | V | |||
VIN = 20 V | 2.3 | |||||
tSTART | Start-up time | From VEN > VEN(ON) to VOUT ≥ 98% of VOUT(NOM) | 155 | 300 | µs | |
PSRR | Power Supply Rejection Ratio | VOUT = 1.2 V, f = 10 kHz | 110 | dB | ||
VOUT = 5 V, f = 10 kHz | 90 | |||||
VOUT = 1.2 V, f = 100 kHz | 90 | |||||
VOUT = 5 V, f = 100 kHz | 60 | |||||
VOUT = 1.2 V, f = 1 MHz | 70 | |||||
VOUT = 5 V, f = 1 MHz | 60 | |||||
eN | Output noise voltage (RMS) | VIN = 3 V, VOUT = 1.2 V COUT = 1 µF X7R BW = 10 Hz to 100 kHz |
4.96 | µV(RMS) | ||
VIN = 3 V, VOUT = 1.2 V BW = 10 Hz to 100 kHz |
5.21 | |||||
VIN = 3 V, VOUT = 1.2 V BW = 10 Hz to 10 MHz |
11.53 | |||||
VIN = 6 V, VOUT = 5 V COUT = 1 µF X7R BW = 10 Hz to 100 kHz |
5.38 | |||||
VIN = 6 V, VOUT = 5 V BW = 10 Hz to 100 kHz |
5.43 | |||||
VIN = 6 V, VOUT = 5 V BW = 10 Hz to 10 MHz |
11.58 | |||||
ENABLE INPUT | ||||||
VEN(ON) | Enable ON threshold voltage | VEN rising from 500 mV until Output is ON | 1.14 | 1.24 | 1.34 | V |
ΔVEN | Enable threshold voltage hysteresis | VEN falling from VEN(ON) | 110 | mV | ||
IEN(IL) | EN pin pullup current | VEN = 500 mV | 2 | 3 | µA | |
IEN(IH) | EN pin pullup current | VEN = 2 V | 2 | 3 | ||
VEN(CLAMP) | Enable pin clamp voltage | EN pin = Open | 5 | V | ||
THERMAL SHUTDOWN | ||||||
TSD | Thermal shutdown | Junction temperature (TJ) rising | 170 | °C | ||
ΔTSD | Thermal shutdown hysteresis | Junction temperature (TJ) falling from TSD | 12 |
The LP38798 is a positive voltage (20 V), ultra-low-noise (5 µVRMS), low-dropout (LDO) regulator capable of supplying a well-regulated, low-noise voltage to an 800-mA load. The LP38798 uses an advanced design with a CMOS process to deliver ultra low output noise and high PSRR at switching power supply (SMPS) frequencies.
Any noise at LP38798 SET pin is reduced by an internal passive, first order low-pass RC filter before it is passed to the output buffer stage. The low-pass filter has a –3-dB cut-off frequency of approximately 0.08 Hz.
To keep the low-pass filter from interfering with the output voltage rise time at start-up, a voltage comparator keeps the filter in a fast-charge mode while the output voltage (VOUT) is less than 99.5% of the SET pin voltage (VSET) . When the rising VOUT is within 0.5% of VSET the fast-charge mode ends, and VOUT will rise the final 0.5% based on the RC time constant (τ = 2s) of the filter.
Should VOUT be more than 2% above the VSET voltage, a voltage comparator will put the filter into the fast-charge mode to allow the filter to discharge and VOUT to fall a value closer to VSET. When the falling VOUT is within 2% of VSET the fast-charge mode ends, and VOUT will fall the final 2% based on the RC time constant (τ = 2s) of the filter.
If the input voltage has an extended rise time, the output voltage may exhibit a stair-case waveform as the fast-charge mode is activated and de-activated as VSET rises with VIN, and VOUT follows. Once the VIN has risen above the programmed VSET voltage, and VOUT is within 0.5% of VSET, the stair-case behavior will end.
The Enable pin (EN) is pulled high internally by a 2 μA (typical) current source from the IN pin, and internally clamped at 5 V (typical) by a zener. Pulling the EN pin low, by sinking the IEN current to ground, will turn the output off.
If the EN function is not needed the EN pin should be left open (floating). Do not connect the EN pin directly to VIN if there is any possibility that VIN might exceed 5.5 V (that is, EN pin AbsMax). If external pullup is required, the external current into the EN pin should be limited to no more than 10 μA.
The LP38798 incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the LP38798 disabled while a rising VIN is less than 2.65 V (typical). The rising UVLO threshold is approximately 350 mV below the recommended minimum operating VIN of 3 V.
The LP38798 incorporates active output current limiting. The threshold for the output current limiting is set well above the ensured output operating current such that it does not interfere with normal operation.
Note that output current limiting is provided as a safety feature and is outside the recommended operating conditions. Operation at the current limit is not recommended as the device junction temperature (TJ) will rise rapidly and operation will likely cross into thermal shutdown behavior .
The LP38798 includes thermal protection that will shut-off the output current when activated by excessive device dissipation. Thermal shutdown (TSD) will occur when the junction temperature has risen to 170°C. The junction temperature must fall typically 12°C from the shutdown temperature for the output current to be restored. Junction temperature is calculated from the formula in Equation 2:
Where the power being dissipated, PD, is defined as:
NOTE
Thermal shutdown is provided as a safety feature and is outside the specified Operating Ratings temperature range. Operation with a junction temperature (TJ) above 125°C is not recommended as the device behavior is not specified.
The LP38798 has two functional modes:
Current sourced from the SET pin, through R1 and R2, must be kept to less than 100 µA. The minimum allowed value for R2 is 12.9 kΩ.
The values for R1 and R2 may be adjusted as needed to achieve the desired output voltage as long as the value for R2 is no less than 12.9 kΩ. The maximum recommended value for R2 is 100 kΩ.
Equation 7 is used to determine the output voltage:
Alternately, Equation 8 can be used to determine the appropriate R1 value for a given R2 value:
Table 1 suggests some ±1% values for R1 and R2 for a range of output voltages using the typical VFB value of 1.200V. This is not a definitive list, as other combinations exist that will provide similar, possibly better, performance.
TARGET VOUT | R1 | R2 | TYPICAL VOUT |
---|---|---|---|
1.2 V | 0 Ω | 15 kΩ | 1.2 V |
1.5 V | 4.22 kΩ | 16.9 kΩ | 1.5 V |
1.8 V | 10.5 kΩ | 21 kΩ | 1.8 V |
2 V | 10 kΩ | 15 kΩ | 2 V |
2.5 V | 16.2 kΩ | 15.0 kΩ | 2.496 V |
3 V | 21 kΩ | 14 kΩ | 3 V |
3.3 V | 23.2 kΩ | 13.3 kΩ | 3.293 V |
5 V | 47.5 kΩ | 15 kΩ | 5 V |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LP38798 is a high-performance linear regulator capable of supplying a well-regulated, low-noise voltage into an 800-mA load. The LP38798 can operate over a wide input voltage range (3 V to 20 V) making it well suited for many post-regulation applications.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage | 5.5 V, ±10% |
Output voltage | 5. V, ±3.5% |
Output current | 500 mA |
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The LP38798 is designed and characterized for operation with a ceramic capacitor of 1 µF, or greater, at the input. Note especially that the input capacitances must be located as near as practical to the IN pins
The minimum recommended input capacitance is 1 µF, ceramic or tantalum. However, if the LP38798 is operating in conditions where input ripple, fast changes in the input voltage, or large changes in the load current demand are expected, a minimum input capacitance of 10 µF is strongly recommended
Ceramic capacitor tolerance and variations due temperature and applied voltage must be considered when selecting a capacitor to assure the minimum input capacitance requirement is met over the intended operating range.
The input capacitor must be located as close as physically possible to the input pin and returned to a clean analog ground. Any good quality tantalum capacitor may be used, while a ceramic capacitor should be X5R or X7R rated with appropriate adjustments due to the loss of capacitance value from the applied DC voltage.
Attention must be given to the input capacitance value to minimize transient input voltage droop during load current steps at the OUT pin. Larger input capacitor values are necessary for good transient load response, and have no detrimental influence on the stability of the device. Note, however, that using large value ceramic input capacitances can also cause unwanted ringing at the output if the input capacitor, in combination with the trace inductance, creates a high-Q peaking effect during transients. Short, well-designed interconnect leads to the up-stream supply minimize this effect without adding damping. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred milli-ohms of ESR, in parallel with the ceramic input capacitor.
The LP38798 requires an output capacitance of at least 1 µF, ceramic or tantalum; however, a minimum output capacitance of 10 µF is strongly recommended if fast load transient conditions are expected. While the LP38798 is designed to work with Ceramic output capacitors, the output capacitor can be Ceramic, Tantalum, or a combination. The total output capacitance must be sized appropriately to handle any fast load current steps. Capacitance type, tolerance, ESR, as well as temperature and voltage characteristics, must be considered when selecting an output capacitor for the application.
Note especially that the output capacitances must be located as near as practical to the OUT pins.
Even though the LP38798 is stable with an output capacitance of 1 µF to 10 µF, a single output capacitor will generally not be able to provide the best PSRR performance across a wide frequency range. Multiple parallel capacitors, each with a different self-resonance frequency will provide better performance over a wider frequency range.
The LP38798 is characterized with a ceramic capacitor of 10 µF, or greater, at the output. Noise performance is characterized using a single output capacitor of 10 µF ±10%, 16V, X7R, 1206.
The charge pump is running when both the input voltage is above the UVLO threshold (2.65 V typical) and the EN pin voltage is above the VEN(ON) threshold (1.24 V typical). The typical charge pump operating frequency is 3.5 MHz.
A low leakage 10 nF X7R storage capacitor is required between the CP pin and ground to store the energy required for gate drive of the internal NMOS pass device. Larger values of capacitance may slow start-up times, while smaller capacitance values may result in degraded dynamic performance.
Do not make any other connection to the CP pin. Loading this pin in any manner degrades regulator performance. No external biasing may be applied to, or derived from, this pin, as permanent damage to the internal charge pump circuitry may occur.
The output voltage is buffered from the SET pin. The output voltage is defined as:
Selecting a standard 1% resistor value of 15 kΩ for R2, the resistor value needed for R1 to provide an output voltage of 5V is calculated from:
Device power dissipation is defined as:
Given 250 mW of device power dissipation, a maximum operating junction temperature (TJ) of 125°C, and presuming a RθJA of 35.4°C/W, the maximum ambient temperature (TA) is defined as:
The LP38798 device is designed to operate from an input voltage supply range of 3 V to 20 V. The input supply must be able to supply enough current to keep the input voltage from drooping during load transients and high load current. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.