SN65HVD63 AISG® On and Off Keying Coax Modem Transceiver
- SLLSEO3 July 2015 SN65HVD63
  
  PRODUCTION DATA.

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DATA SHEET

SN65HVD63 AISG® On and Off Keying Coax Modem Transceiver

1 Features

3-V to 5.5-V Supply Range
1.6-V to 5.5-V Independent Logic Supply
–15-dBm to +5-dBm Wide-Input Dynamic Range
for Receiver
0-dBm to 6-dBm Adjustable Power
Delivered by the Driver to the Coax
AISG® V2.0-Compliant Output Emission Profile
Also Conforms to Proposed AISG V3.0 Specifications
Low-Power Standby Mode
Direction Control Output
for RS-485 Bus Arbitration
Up to 115 kbps of Signaling Support
2.176-MHz Center Frequency
for Integrated Active Bandpass Filter
3-mm × 3-mm 16-Pin VQFN Package

2 Applications

AISG – Interface for Antenna Line Devices
Tower-Mounted Amplifiers (TMA)
General Modem Interfaces

3 Description

The SN65HVD63 transceiver modulates and demodulates signals between a logic (baseband) interface and a frequency suitable for long coaxial media, to facilitate wired data transfer among radio equipment.

The SN65HVD63 device is an integrated AISG transceiver designed to meet the requirements of the upcoming Antenna Interface Standards Group v3.0 specification.

The SN65HVD63 receiver integrates an active bandpass filter to enable demodulation of signals even in the presence of spurious frequency components. The filter has a 2.176-MHz center frequency.

The transmitter supports adjustable output power levels from 0 dBm to 6 dBm delivered to the 50-Ω coax cable. The SN65HVD63 transmitter is compliant with the spectrum emission requirement provided by the AISG standard.

A direction control output facilitates bus arbitration for an RS-485 interface. This device integrates an oscillator input for a crystal, and also accepts standard clock inputs to the oscillator.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
SN65HVD63	VQFN (16)	3.00 mm × 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

4 Revision History

DATE	REVISION	NOTES
July 2015	*	Initial release.

5 Device Comparison Table

PART NUMBER	STANDARD SUPPORTED	SPURIOUS FREQUENCY RANGE	MAXIMUM LEVEL
SN65HVD62	AISG 2.0	≤ 1.1 MHz	2 dBm (793 mV_PP)
SN65HVD62	AISG 2.0	≤ 4.17 MHz	2 dBm (793 mV_PP)
SN65HVD63	AISG 3.0	≤ 1.35 MHz	–13 dBm (142 mV_PP)
SN65HVD63	AISG 3.0	≤ 3.5 MHz	–13 dBm (142 mV_PP)

6 Pin Configuration and Functions

RGT Package

16-Pin VQFN With Exposed Thermal Pad

Top View

Pin Functions

PIN			DESCRIPTION
NAME	NO.	TYPE	DESCRIPTION
BIAS	10	O	Bias voltage output for setting driver output power by external resistors
DIR	5	O	Direction control output signal for bus arbitration
DIRSET1	7	—	DIRSET1 and DIRSET2: Bits to set the duration of DIR DIRSET[2:1]: [L:L] = 9.6 kbps; [L:H] = 38.4 kbps; [H:L] = 115 kbps; [H:H] = standby mode
DIRSET2	6	—
GND	8	—	Ground
GND	16	—	Ground
RES	9	P	Input voltage to adjust driver output power that is set by external resistors from BIAS pin to GND
RXIN	11	I	Modulated input signal to the receiver
RXOUT	4	O	Digital data bit stream from receiver
SYNCOUT	1	O	Open-drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1 and XTAL2
TXIN	2	I	Digital data bit stream to driver
TXOUT	12	O	Modulated output signal from the driver
V_CC	13	P	Analog supply voltage for the device
VL	3	P	Logic supply voltage for the device
XTAL1	14	I/O	I/O pins of the crystal oscillator. Connect a 4 × f_C crystal between these pins or connect XTAL1 to an 8.704-MHz clock and connect XTAL2 to GND.
XTAL2	15	I/O
EP	—	—	Exposed pad. Connection to ground plane is recommended for best thermal conduction.

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, V_CC and VL	–0.5	6	V
Voltage at coax pins	–0.5	6	V
Voltage at logic pins	–0.3	V_VL + 0.3	V
Logic output current	–20	20	mA
TXOUT output current	Internally limited
SYNCOUT output current	Internally limited
Junction temperature, T_J		170	°C
Continuous total power dissipation	See the Thermal Information		°C
Storage temperature, T_stg⁽²⁾	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Applicable before the device is installed in the final product.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC	Analog supply voltage		3		5.5	V
V_L	Logic supply voltage		1.6		5.5	V
V_I(pp)	Input signal amplitude at RXIN				1.12	Vpp
V_IH	High-level input voltage	TXIN, DIRSET1, DIRSET2	70%V_L		V_L	V
V_IH	High-level input voltage	XTAL1, XTAL2	70%V_CC		V_CC	V
V_IL	Low-level input voltage	TXIN, DIRSET1, DIRSET2	0		30%V_L	V
V_IL	Low-level input voltage	XTAL1, XTAL2	0		30%V_CC	V
1/t_UI	Data signaling rate		9.6		115	kbps
F_OSC	Oscillator frequency		–30 ppm	8.704	30 ppm	MHz
Z_LOAD	Load impedance between TXOUT to RXIN			50		Ω
Z_LOAD	Load impedance between RXIN and GND at f_C (channel)			50		Ω
R1	Bias resistor between BIAS and RES			4.1		kΩ
R2	Bias resistor between RES and GND			10		kΩ
R_SYNC	Pullup resistor between SYNCOUT and V_CC			1		kΩ
V_RES	Voltage at RES pin		0.7		1.5	V
C_C	Coupling capacitance between RXIN and coax (channel)			220		nF
C_BIAS	Capacitance between BIAS and GND			1		µF
T_A	Operating free-air temperature		–40		105	°C
T_J	Junction temperature		–40		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		VQFN	UNIT
THERMAL METRIC⁽¹⁾		RGT16 Pins	UNIT
R_θJA	Junction-to-ambient thermal resistance	49.4	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	64.2	°C/W
R_θJB	Junction-to-board thermal resistance	22.9	°C/W
ψ_JT	Junction-to-top characterization parameter	1.7	°C/W
ψ_JB	Junction-to-board characterization parameter	22.9	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	25	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
I_CC	Supply current	DIRSET1 = L DIRSET2 = H	TXIN = L (active)		28	33	mA
			TXIN = H (quiescent)		25	31
			TXIN = 115 kbps, 50% duty cycle		27	33
		DIRSET1 = H, DIRSET2 = H (standby)			12	17
I_VL	Logic supply current	TXIN = H, RXIN = DC input				50	µA
PSRR	Receiver power supply rejection ratio	V_TXIN = V_L		45	60		dB
LOGIC PINS
V_OH	High-level logic output voltage (RXOUT, DIR)	I_OH = –4 mA for V_L > 2.4 V, I_OH = –2 mA for V_L < 2.4 V		90%V_VL			V
V_OL	Low-level logic output voltage (RXOUT, DIR)	I_OL = 4 mA for V_L > 2.4 V, I_OL = 2 mA for V_L < 2.4 V				10%V_VL	V
COAX DRIVER
V_O(PP)	Peak-to-peak output voltage at device pin TXOUT (see Figure 19)	V_RES = 1.5 V (Maximum setting)		2.24	2.5		V_PP
V_O(PP)		V_RES = 0.7 V (Minimum setting)			1.17	1.3	V_PP
V_O(PP)	Peak-to-peak voltage at coax out (see Figure 19)	V_RES = 1.5 V		5	6		dBm
V_O(PP)	Peak-to-peak voltage at coax out (see Figure 19)	V_RES = 0.7 V			–0.6	0.3	dBm
V_O(OFF)	Off-state output voltage	At TXOUT				1	mVpp
V_O(OFF)	Off-state output voltage	At coax out				–60	dBm
	Output emissions	Coupled to coaxial cable with characteristic impedance of 50 Ω, as shown in Figure 1⁽¹⁾⁽²⁾					N/A
f_O	Output frequency				2.176		MHz
∆f	Output frequency variation			–100		100	ppm
Z_O	Output impedance	At 100 kHz			0.03		Ω
Z_O	Output impedance	At 10 MHz			3.5		Ω
\| I_OS \|	Short-circuit output current	TXOUT is also protected by a thermal shutdown circuit during short-circuit faults			300	450	mA
COAX RECEIVER
V_IT	Input threshold	f_IN = 2.176 MHz		79	112	158	mVPP
V_IT	Input threshold	f_IN = 2.176 MHz		–18	–15	–12	dBm
Z_IN	Input impedance	f = f_O		11	21		kΩ
RECEIVER FILTER
f_PB	Passband	VRXIN = 1.12VP_P		1.1		4.17	MHz
f_REJ	Receiver rejection range	2.176-MHz carrier amplitude of 112.4 mV_PP, frequency band of spurious components with 800 mVPP allowed.		1.1		4.17	MHz
t_{noise filter}	Receiver noise filter time (slow bit rate)	DIRSET for 9.6 kbps			4		µs
t_{noise filter}	Receiver noise filter time (fast bit rate)	DIRSET for > 9.6 kbps			2		µs
XTAL AND SYNC
I_I	Input leakage current	XTAL1, XTAL2, 0V < V_IN < V_CC		–15		15	µA
V_OL	Output low voltage	SYNCOUT, with 1-kΩ resistor from SYNCOUT to V_CC				0.4	V

(1) Specified by design with a recommended 470-pF capacitor between RXIN and GND. Measurements above 150 MHz are determined by setup.

(2) Conforms to AISG spectrum emissions mask, 3GPP TS 25.461, see Figure 21.

7.6 Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_pAQ, t_pQA	Coax driver propagation delay	See Figure 19			5	µs
t_r, t_f	Coax receiver output rise/fall time	C_L = 15 pF, R_L = 1 kΩ; see Figure 19			20	ns
t_PHL, t_PLH	Receiver propagation delay	See Figure 20		5.5	11	µs
	Coax receiver output duty cycle	V_RXIN(ON) = 630 mVpp, V_RXIN(OFF) < 5 mVpp, 50% duty cycle	40%		60%
	Coax receiver output duty cycle	V_RXIN(ON) = 200 mVpp, V_RXIN(OFF) < 5 mVpp, 50% duty cycle	40%		60%
t_DIR	Direction control active duration	DIRSET2 = GND or OPEN, DIRSET1 = GND or OPEN		1667		µs
		DIRSET2 = GND, DIRSET1 = VL		417
		DIRSET2 = VL, DIRSET1 = VL		137
t_DIRSKEW	Direction control skew (DIR to RXOUT)		270			ns
t_dis	Standby disable delay	300 mV_PP at 2.176 MHz on RXIN		2		ms
t_en	Standby enable delay	300 mV_PP at 2.176 MHz on RXIN		2		ms

7.7 Typical Characteristics

50% Duty Cycle

C_F = 470 pF

Figure 1. Low-Frequency Emissions Spectrum
With 9.6-kbps Signaling Rate

50% Duty Cycle

C_F = 470 pF

Figure 3. Low-Frequency Emissions Spectrum
With 38.4-kbps Signaling Rate

50% Duty Cycle

C_F = 470 pF

Figure 5. Low-Frequency Emissions Spectrum
With 115.2-kbps Signaling Rate

Figure 7. Transmitter Output Impedance

TXIN = VL

Figure 9. Supply Current vs Supply Voltage
While Transmitting

Figure 11. Supply Current vs Temperature
in Standby Mode

Figure 13. Transmitter Output Power vs Temperature

Figure 15. Receiver Input Threshold vs Temperature

Figure 17. Receiver Duty Cycle
With 9.6 kbps Signaling Rate

50% Duty Cycle

C_F = 470 pF

Figure 2. High-Frequency Emissions Spectrum
With 9.6-kbps Signaling Rate

50% Duty Cycle

C_F = 470 pF

Figure 4. High-Frequency Emissions Spectrum
With 38.4-kbps Signaling Rate

50% Duty Cycle

C_F = 470 pF

Figure 6. High-Frequency Emissions Spectrum
With 115.2-kbps Signaling Rate

Figure 8. Transmit Power Adjustment

TXIN = VL

Figure 10. Supply Current vs Supply Voltage
in Standby Mode

Figure 12. Transmitter Output Power
vs Supply Voltage

Figure 14. Receiver Input Impedance vs Frequency

Figure 16. DIR Output Delay vs Temperature

Figure 18. Receiver Duty Cycle
With 115.2 kbps Signaling Rate

8 Parameter Measurement Information

Signal generator rate is 115 kbps, 50% duty cycle. Rise and fall times are less than 6 ns, and nominal output levels are 0 V and 3 V. Coupling capacitor, C_C, is 220 nF.

Figure 19. Measurement of Modem Driver
Output Voltage With 50-Ω Loads

Figure 20. Measurement of Modem Receiver Propagation Delays

SN65HVD63 emissions_template_sllseo3.png

Figure 21. AISG Emissions Template

9 Detailed Description

9.1 Overview

The SN65HVD63 transceiver modulates and demodulates signals between the logic (baseband) and a frequency suitable for long coaxial media. The SN65HVD63 device is an integrated AISG transceiver designed to meet the requirements of the upcoming Antenna Interface Standards Group v3.0 specification. The SN65HVD63 receiver integrates an active bandpass filter to enable demodulation of signals even in the presence of spurious frequency components. The filter has a 2.176-MHz center frequency. The transmitter supports adjustable output power levels from 0 dBm to 6 dBm delivered to the 50-Ω coax cable. The SN65HVD63 transmitter is compliant with the spectrum emission requirement provided by the AISG standard. A direction control output facilitates bus arbitration for an RS-485 interface. This device integrates an oscillator input for a crystal, and also accepts standard clock inputs to the oscillator.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Coaxial Interface

The SN65HVD63 transceiver enables the transfer of data between radio equipment by modulating baseband data to a carrier frequency of 2.176 MHz (per the AISG standard). The transmitter output amplitude can be configured from 0 dBm to 6 dBm in order to communicate over a variety of different links, and the output emissions spectrum is designed to be compliant to AISG limits. The receiver features an active bandpass filter circuit that helps to separate the carrier frequency data from other spurious frequency components.

9.3.2 Reference Input

The 2.176-MHz modulation frequency is derived from an input reference that is nominally 8.704 MHz. The input reference can come either from a crystal or from an oscillator circuit with a tolerance of up to 30 ppm.

9.3.3 RS-485 Direction Control

To facilitate bus arbitration of an RS-485 interface, the SN65HVD63 provides a direction control output that can be used to control the enable/disable controls of an RS-485 transceiver. The direction control output automatically toggles based on activity present on the coaxial input interface, and has an adjustable time constant (controlled by the DIRSET1 and DIRSET2 pins) in order to accommodate various signaling rates.

9.4 Device Functional Modes

If DIRSET1 and DIRSET2 are in a logic high state, the device will be in standby mode. While in standby mode, the receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the RXOUT state. The transmitter circuits are not active in standby mode, thus the TXOUT pin is idle regardless of the logic state of TXIN. The supply current in standby mode is significantly reduced, allowing power savings when the node is not transmitting.

When not in standby mode, the default power-on state is idle. When in idle mode, RXOUT is high, and TXOUT is quiet. The device transitions to receive mode when a valid modulated signal is detected on the RXIN line or the device transitions to transmit mode when TXIN goes low. The device stays in either receive or transmit mode until DIR time-out (nominal 16 bit times) after the last activity on RXOUT or TXIN.

When in receive mode:

RXOUT responds to all valid modulated signals on RXIN, whether from the local transmitter, a remote transmitter, or long noise burst.
TXOUT responds to TXIN, generating 2.176-MHz signals on TXOUT when TXIN is low, and TXOUT is quiet when TXIN is high. (In normal operation, TXIN is expected to remain high when the device is in receive mode.)
The device stays in receive mode until 16 bit times after the last rising edge on RXOUT, caused by valid modulated signal on the RXIN line.

When in transmit mode:

RXOUT stays high, regardless of the input signal on RXIN.
TXOUT responds to TXIN, generating 2.176-MHz signals on TXOUT when TXIN is low, and TXOUT is quiet when TXIN is high.
The device stays in transmit mode until 16 bit times after TXIN goes high.

Table 1 shows the driver functions. Table 2 shows the receiver functions. Figure 22 shows the transitions between each state.

Table 1. Driver Function Table

TXIN⁽¹⁾	[DIRSET1, DIRSET2]	TXOUT	COMMENT
H	[L,L], [L,H] or [H,L]	< 1 mV_PP at 2.176 MHz	Driver not active
L	[L,L], [L,H] or [H,L]	V_OPP at 2.176 MHz	Driver active
X	[H,H]	< 1 mV_PP at 2.176 MHz	Standby mode

(1) H = High, L = Low, X = Indeterminate

Table 2. Receiver and DIR Function Table

RXIN⁽¹⁾	RXOUT	DIR	COMMENT (see Figure 22)
IDLE mode (not transmitting or receiving)
< V_IT at 2.176 MHz for longer than DIR time-out	H	L	No outgoing or incoming signal
RECEIVE mode (not already transmitting)
< V_IT at 2.176 MHz for less than t_{DIR time-out}	H	H	Incoming 1 bit, DIR stays HIGH for DIR time-out
> V_IT at 2.176 MHz for longer than t_{noise filter}	L	H	Incoming 0 bit, DIR output is HIGH
TRANSMIT mode (not already receiving)
X	H	L	Outgoing message, DIR stays LOW for DIR time-out

(1) H = High, L = Low, X = Indeterminate

Figure 22. State Transition Diagram

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 Driver Amplitude Adjust

The SN65HVD63 device can provide up to 2.5 V of peak-to-peak output signal at the TXOUT pin to compensate for potential loss within the external filter, cable, connections, and termination. External resistors are used to set the amplitude of the modulated driver output signal. Resistors connected across RES and BIAS set the output amplitude. The maximum peak-to-peak voltage at TXOUT is 2.5 V, corresponding to 6 dBm on the coaxial cable. The TXOUT voltage level can be adjusted by choice of resistors to set the voltage at the RES pin. according to the following equation:

Equation 1. VTXOUT (V_PP) = (2.5 V_PP × V_RES (V)) / 1.5 V V_RES (V) = 1.5 V × R2 / (R1 + R2) V_TXOUT (V_PP) = 2.5 V_PP × R2 / (R1 + R2)

The voltage at the RES pin should be from 0.7 V to 1.5 V. Connect RES directly to the BIAS (R1 = 0 Ω) for maximum output level of 2.5 VPP. This gives a minimum voltage level at TXOUT of 1.2 VPP, corresponding to about 0 dBm at the coaxial cable. A 1-μF capacitor should be connected between the BIAS pin and GND. To obtain a nominal power level of 3 dBm at the feeder cable as the AISG standard requires, use R1 = 4.1 kΩ and R2 = 10 kΩ that provide 1.78 V_PP at TXOUT.

10.1.2 Direction Control

In many applications the mast-top modem that receives data from the base distributes the received data through an RS-485 network to several mast-top devices. When the mast-top modem receives the first logic 0 bit (active modulated signal) it takes control of the mast-top RS-485 network by asserting the direction control signal. The duration of the direction control assertion should be optimized to pass a complete message of length B bits at the known signaling rate (1/t_BIT) before relinquishing control of the mast-top RS-485 network. For example, if the messages are 10 bits in length (B=10) and the signaling rate is 9600 bits per second (t_BIT = 0.104 ms) then a positive pulse of duration 1.7 ms is sufficient (with margin to allow for network propagation delays) to enable the mast-top RS-485 drivers to distribute each received message. Figure 23 shows the assertion of direction control.

Figure 23. Assertion of Direction Control

10.1.3 Direction Control Time Constant

The time constant for the direction control function can be set by the control mode pins, DIRSET1 and DIRSET2. These pins should be set to correspond to the desired data rate. With no external connections to the control mode pins, the internal time constant is set to the maximum value, corresponding to the minimum data rate.

10.1.4 Conversion Between dBm and Peak-to-Peak Voltage

Equation 2. dBm = 20 × LOG10 [Volts-pp / SQRT(0.008 × Z_o)] = 20 × LOG10 [VPP / 0.63] for Z_o = 50 Ω

Equation 3. VPP = SQRT(0.008 × Z_o) × 10^(dBm/20) = 0.63 × 10^(dBm/20) for Z_o = 50 Ω

Table 3 shows conversions between dBm and peak-to-peak voltage with a 50-Ω load, for various levels of interest including reference levels from the 3GPP TS 25.461 Technical Specification.

Table 3. Conversions Between dBM and Peak-to-Peak Voltage

SIGNAL ON COAX	dBm	V_PP
Maximum Driver ON Signal	5	1.12
Nominal Driver ON Signal	3	0.89
Minimum Driver ON Signal	1	0.71
AISG Maximum Receiver Threshold	–12	0.16
Nominal Receiver Threshold	–15	0.11
Minimum Receiver Threshold	–18	0.08
Maximum Driver OFF Signal	–40	0.006

10.2 Typical Application

The AISG On-Off Keying (OOK) interface allows for command, control, and diagnostic information to be communicated between a base station and the corresponding tower-mounted antennae. Figure 24 shows a typical application.

Figure 24. Typical AISG Application

10.2.1 Design Requirements

An AISG transceiver is used to convert between digital logic-level signals and RF signals. The AISG standard requires an RF carrier frequency of 2.176 MHz with 100-ppm accuracy. The output signal of the driver, when active, should be from 1 dBm to 5 dBm. The receiver must be designed such that the input threshold is from –18 dBm to –12 dBm.

10.2.2 Detailed Design Procedure

To ensure accuracy of the carrier frequency, an input reference frequency equal to four times the carrier (that is, 8.704 MHz) should be connected to the XTAL1 or XTAL2 inputs. This signal can come from a crystal (connected between XTAL1 and XTAL2) or from a PLL/clock generator circuit (connected to XTAL1 with XTAL2 grounded). The frequency accuracy must be within 100 ppm.

The driver output power level of the SN65HVD63 device can be adjusted through use of the RES pin. To align with AISG requirements, a nominal power level of 3 dBm should be configured by connecting a 4.1-kΩ resistor between RES and BIAS and a 10-kΩ resistor between RES and GND. Figure 25 shows an example schematic.

Figure 25. SN65HVD63 Schematic

10.2.3 Application Curve

Figure 26 shows the application curve for the SN65HVD63 device.

SN65HVD63 Time_Domain_Waveforms_115p2-kbps_Trans_SLLSEO3.png

Figure 26. SN65HVD63 Application Curve

11 Power Supply Recommendations

The SN65HVD63 device has two power supply pins: V_CC, which provides power to the analog circuitry, and VL, which is a logic supply. V_CC should be operated from 3 V to 5.5 V, while VL can range from 1.6 V to 5.5 V to interface to different logic levels. Power supply decoupling capacitances of at least 0.1 µF should be placed as close as possible to each power supply pin.

12 Layout

12.1 Layout Guidelines

Best practices for high-speed PCB design should be observed because the coax interface to the SN65HVD63 device operates at RF. The RF signaling traces should have a controlled characteristic impedance that is well-matched to the coaxial line. A continuous reference plane should be used to avoid impedance discontinuities. Power and ground distribution should be done through planes rather than traces to decrease series resistance and increase the effective decoupling capacitance on the power rails.

12.2 Layout Example

SN65HVD63 HVD63_Layout_Example_Top_SLLSEO3.gif

Figure 27. SN65HVD63 Layout

13 Device and Documentation Support

13.1 Related Documentation

Control Interface for Antenna Line Devices, Antenna Interface Standards Group, Standard No. AISG v2.0

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support

TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

13.3 Trademarks

E2E is a trademark of Texas Instruments.

AISG is a registered trademark of Antenna Interface Standards Group, Ltd.

All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.

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