The SN65HVD63 transceiver modulates and demodulates signals between a logic (baseband) interface and a frequency suitable for long coaxial media, to facilitate wired data transfer among radio equipment.
The SN65HVD63 device is an integrated AISG transceiver designed to meet the requirements of the upcoming Antenna Interface Standards Group v3.0 specification.
The SN65HVD63 receiver integrates an active bandpass filter to enable demodulation of signals even in the presence of spurious frequency components. The filter has a 2.176-MHz center frequency.
The transmitter supports adjustable output power levels from 0 dBm to 6 dBm delivered to the 50-Ω coax cable. The SN65HVD63 transmitter is compliant with the spectrum emission requirement provided by the AISG standard.
A direction control output facilitates bus arbitration for an RS-485 interface. This device integrates an oscillator input for a crystal, and also accepts standard clock inputs to the oscillator.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN65HVD63 | VQFN (16) | 3.00 mm × 3.00 mm |
DATE | REVISION | NOTES |
---|---|---|
July 2015 | * | Initial release. |
PART NUMBER | STANDARD SUPPORTED | SPURIOUS FREQUENCY RANGE | MAXIMUM LEVEL |
---|---|---|---|
SN65HVD62 | AISG 2.0 | ≤ 1.1 MHz | 2 dBm (793 mVPP) |
≤ 4.17 MHz | 2 dBm (793 mVPP) | ||
SN65HVD63 | AISG 3.0 | ≤ 1.35 MHz | –13 dBm (142 mVPP) |
≤ 3.5 MHz | –13 dBm (142 mVPP) |
PIN | DESCRIPTION | ||
---|---|---|---|
NAME | NO. | TYPE | |
BIAS | 10 | O | Bias voltage output for setting driver output power by external resistors |
DIR | 5 | O | Direction control output signal for bus arbitration |
DIRSET1 | 7 | — | DIRSET1 and DIRSET2: Bits to set the duration of DIR DIRSET[2:1]: [L:L] = 9.6 kbps; [L:H] = 38.4 kbps; [H:L] = 115 kbps; [H:H] = standby mode |
DIRSET2 | 6 | — | |
GND | 8 | — | Ground |
16 | |||
RES | 9 | P | Input voltage to adjust driver output power that is set by external resistors from BIAS pin to GND |
RXIN | 11 | I | Modulated input signal to the receiver |
RXOUT | 4 | O | Digital data bit stream from receiver |
SYNCOUT | 1 | O | Open-drain output to synchronize other devices to the 4x-carrier oscillator at XTAL1 and XTAL2 |
TXIN | 2 | I | Digital data bit stream to driver |
TXOUT | 12 | O | Modulated output signal from the driver |
VCC | 13 | P | Analog supply voltage for the device |
VL | 3 | P | Logic supply voltage for the device |
XTAL1 | 14 | I/O | I/O pins of the crystal oscillator. Connect a 4 × fC crystal between these pins or connect XTAL1 to an 8.704-MHz clock and connect XTAL2 to GND. |
XTAL2 | 15 | ||
EP | — | — | Exposed pad. Connection to ground plane is recommended for best thermal conduction. |
MIN | MAX | UNIT | |
---|---|---|---|
Supply voltage, VCC and VL | –0.5 | 6 | V |
Voltage at coax pins | –0.5 | 6 | V |
Voltage at logic pins | –0.3 | VVL + 0.3 | V |
Logic output current | –20 | 20 | mA |
TXOUT output current | Internally limited | ||
SYNCOUT output current | Internally limited | ||
Junction temperature, TJ | 170 | °C | |
Continuous total power dissipation | See the Thermal Information | °C | |
Storage temperature, Tstg(2) | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Analog supply voltage | 3 | 5.5 | V | ||
VL | Logic supply voltage | 1.6 | 5.5 | V | ||
VI(pp) | Input signal amplitude at RXIN | 1.12 | Vpp | |||
VIH | High-level input voltage | TXIN, DIRSET1, DIRSET2 | 70%VL | VL | V | |
XTAL1, XTAL2 | 70%VCC | VCC | ||||
VIL | Low-level input voltage | TXIN, DIRSET1, DIRSET2 | 0 | 30%VL | V | |
XTAL1, XTAL2 | 0 | 30%VCC | ||||
1/tUI | Data signaling rate | 9.6 | 115 | kbps | ||
FOSC | Oscillator frequency | –30 ppm | 8.704 | 30 ppm | MHz | |
ZLOAD | Load impedance between TXOUT to RXIN | 50 | Ω | |||
Load impedance between RXIN and GND at fC (channel) | 50 | Ω | ||||
R1 | Bias resistor between BIAS and RES | 4.1 | kΩ | |||
R2 | Bias resistor between RES and GND | 10 | kΩ | |||
RSYNC | Pullup resistor between SYNCOUT and VCC | 1 | kΩ | |||
VRES | Voltage at RES pin | 0.7 | 1.5 | V | ||
CC | Coupling capacitance between RXIN and coax (channel) | 220 | nF | |||
CBIAS | Capacitance between BIAS and GND | 1 | µF | |||
TA | Operating free-air temperature | –40 | 105 | °C | ||
TJ | Junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | VQFN | UNIT | |
---|---|---|---|
RGT16 Pins | |||
RθJA | Junction-to-ambient thermal resistance | 49.4 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 64.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 22.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 22.9 | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | 25 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLY | |||||||
ICC | Supply current | DIRSET1 = L DIRSET2 = H |
TXIN = L (active) | 28 | 33 | mA | |
TXIN = H (quiescent) | 25 | 31 | |||||
TXIN = 115 kbps, 50% duty cycle |
27 | 33 | |||||
DIRSET1 = H, DIRSET2 = H (standby) | 12 | 17 | |||||
IVL | Logic supply current | TXIN = H, RXIN = DC input | 50 | µA | |||
PSRR | Receiver power supply rejection ratio | VTXIN = VL | 45 | 60 | dB | ||
LOGIC PINS | |||||||
VOH | High-level logic output voltage (RXOUT, DIR) |
IOH = –4 mA for VL > 2.4 V, IOH = –2 mA for VL < 2.4 V |
90%VVL | V | |||
VOL | Low-level logic output voltage (RXOUT, DIR) |
IOL = 4 mA for VL > 2.4 V, IOL = 2 mA for VL < 2.4 V |
10%VVL | V | |||
COAX DRIVER | |||||||
VO(PP) | Peak-to-peak output voltage at device pin TXOUT (see Figure 19) | VRES = 1.5 V (Maximum setting) | 2.24 | 2.5 | VPP | ||
VRES = 0.7 V (Minimum setting) | 1.17 | 1.3 | |||||
VO(PP) | Peak-to-peak voltage at coax out (see Figure 19) |
VRES = 1.5 V | 5 | 6 | dBm | ||
VRES = 0.7 V | –0.6 | 0.3 | |||||
VO(OFF) | Off-state output voltage | At TXOUT | 1 | mVpp | |||
At coax out | –60 | dBm | |||||
Output emissions | Coupled to coaxial cable with characteristic impedance of 50 Ω, as shown in Figure 1(1)(2) | N/A | |||||
fO | Output frequency | 2.176 | MHz | ||||
∆f | Output frequency variation | –100 | 100 | ppm | |||
ZO | Output impedance | At 100 kHz | 0.03 | Ω | |||
At 10 MHz | 3.5 | ||||||
| IOS | | Short-circuit output current | TXOUT is also protected by a thermal shutdown circuit during short-circuit faults | 300 | 450 | mA | ||
COAX RECEIVER | |||||||
VIT | Input threshold | fIN = 2.176 MHz | 79 | 112 | 158 | mVPP | |
–18 | –15 | –12 | dBm | ||||
ZIN | Input impedance | f = fO | 11 | 21 | kΩ | ||
RECEIVER FILTER | |||||||
fPB | Passband | VRXIN = 1.12VP_P | 1.1 | 4.17 | MHz | ||
fREJ | Receiver rejection range | 2.176-MHz carrier amplitude of 112.4 mVPP, frequency band of spurious components with 800 mVPP allowed. | 1.1 | 4.17 | MHz | ||
tnoise filter | Receiver noise filter time (slow bit rate) | DIRSET for 9.6 kbps | 4 | µs | |||
Receiver noise filter time (fast bit rate) | DIRSET for > 9.6 kbps | 2 | µs | ||||
XTAL AND SYNC | |||||||
II | Input leakage current | XTAL1, XTAL2, 0V < VIN < VCC | –15 | 15 | µA | ||
VOL | Output low voltage | SYNCOUT, with 1-kΩ resistor from SYNCOUT to VCC | 0.4 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tpAQ, tpQA | Coax driver propagation delay | See Figure 19 | 5 | µs | ||
tr, tf | Coax receiver output rise/fall time | CL = 15 pF, RL = 1 kΩ; see Figure 19 | 20 | ns | ||
tPHL, tPLH | Receiver propagation delay | See Figure 20 | 5.5 | 11 | µs | |
Coax receiver output duty cycle | VRXIN(ON) = 630 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle | 40% | 60% | |||
VRXIN(ON) = 200 mVpp, VRXIN(OFF) < 5 mVpp, 50% duty cycle | 40% | 60% | ||||
tDIR | Direction control active duration | DIRSET2 = GND or OPEN, DIRSET1 = GND or OPEN | 1667 | µs | ||
DIRSET2 = GND, DIRSET1 = VL | 417 | |||||
DIRSET2 = VL, DIRSET1 = VL | 137 | |||||
tDIRSKEW | Direction control skew (DIR to RXOUT) |
270 | ns | |||
tdis | Standby disable delay | 300 mVPP at 2.176 MHz on RXIN | 2 | ms | ||
ten | Standby enable delay | 300 mVPP at 2.176 MHz on RXIN | 2 | ms |
50% Duty Cycle | CF = 470 pF |
50% Duty Cycle | CF = 470 pF |
50% Duty Cycle | CF = 470 pF |
TXIN = VL |
50% Duty Cycle | CF = 470 pF |
50% Duty Cycle | CF = 470 pF |
50% Duty Cycle | CF = 470 pF |
TXIN = VL |
Signal generator rate is 115 kbps, 50% duty cycle. Rise and fall times are less than 6 ns, and nominal output levels are 0 V and 3 V. Coupling capacitor, CC, is 220 nF.
The SN65HVD63 transceiver modulates and demodulates signals between the logic (baseband) and a frequency suitable for long coaxial media. The SN65HVD63 device is an integrated AISG transceiver designed to meet the requirements of the upcoming Antenna Interface Standards Group v3.0 specification. The SN65HVD63 receiver integrates an active bandpass filter to enable demodulation of signals even in the presence of spurious frequency components. The filter has a 2.176-MHz center frequency. The transmitter supports adjustable output power levels from 0 dBm to 6 dBm delivered to the 50-Ω coax cable. The SN65HVD63 transmitter is compliant with the spectrum emission requirement provided by the AISG standard. A direction control output facilitates bus arbitration for an RS-485 interface. This device integrates an oscillator input for a crystal, and also accepts standard clock inputs to the oscillator.
The SN65HVD63 transceiver enables the transfer of data between radio equipment by modulating baseband data to a carrier frequency of 2.176 MHz (per the AISG standard). The transmitter output amplitude can be configured from 0 dBm to 6 dBm in order to communicate over a variety of different links, and the output emissions spectrum is designed to be compliant to AISG limits. The receiver features an active bandpass filter circuit that helps to separate the carrier frequency data from other spurious frequency components.
The 2.176-MHz modulation frequency is derived from an input reference that is nominally 8.704 MHz. The input reference can come either from a crystal or from an oscillator circuit with a tolerance of up to 30 ppm.
To facilitate bus arbitration of an RS-485 interface, the SN65HVD63 provides a direction control output that can be used to control the enable/disable controls of an RS-485 transceiver. The direction control output automatically toggles based on activity present on the coaxial input interface, and has an adjustable time constant (controlled by the DIRSET1 and DIRSET2 pins) in order to accommodate various signaling rates.
If DIRSET1 and DIRSET2 are in a logic high state, the device will be in standby mode. While in standby mode, the receiver functions normally, detecting carrier frequency activity on the RXIN pin and setting the RXOUT state. The transmitter circuits are not active in standby mode, thus the TXOUT pin is idle regardless of the logic state of TXIN. The supply current in standby mode is significantly reduced, allowing power savings when the node is not transmitting.
When not in standby mode, the default power-on state is idle. When in idle mode, RXOUT is high, and TXOUT is quiet. The device transitions to receive mode when a valid modulated signal is detected on the RXIN line or the device transitions to transmit mode when TXIN goes low. The device stays in either receive or transmit mode until DIR time-out (nominal 16 bit times) after the last activity on RXOUT or TXIN.
When in receive mode:
When in transmit mode:
Table 1 shows the driver functions. Table 2 shows the receiver functions. Figure 22 shows the transitions between each state.
TXIN(1) | [DIRSET1, DIRSET2] | TXOUT | COMMENT |
---|---|---|---|
H | [L,L], [L,H] or [H,L] | < 1 mVPP at 2.176 MHz | Driver not active |
L | VOPP at 2.176 MHz | Driver active | |
X | [H,H] | < 1 mVPP at 2.176 MHz | Standby mode |
RXIN(1) | RXOUT | DIR | COMMENT (see Figure 22) |
---|---|---|---|
IDLE mode (not transmitting or receiving) | |||
< VIT at 2.176 MHz for longer than DIR time-out | H | L | No outgoing or incoming signal |
RECEIVE mode (not already transmitting) | |||
< VIT at 2.176 MHz for less than tDIR time-out | H | H | Incoming 1 bit, DIR stays HIGH for DIR time-out |
> VIT at 2.176 MHz for longer than tnoise filter | L | H | Incoming 0 bit, DIR output is HIGH |
TRANSMIT mode (not already receiving) | |||
X | H | L | Outgoing message, DIR stays LOW for DIR time-out |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The SN65HVD63 device can provide up to 2.5 V of peak-to-peak output signal at the TXOUT pin to compensate for potential loss within the external filter, cable, connections, and termination. External resistors are used to set the amplitude of the modulated driver output signal. Resistors connected across RES and BIAS set the output amplitude. The maximum peak-to-peak voltage at TXOUT is 2.5 V, corresponding to 6 dBm on the coaxial cable. The TXOUT voltage level can be adjusted by choice of resistors to set the voltage at the RES pin. according to the following equation:
The voltage at the RES pin should be from 0.7 V to 1.5 V. Connect RES directly to the BIAS (R1 = 0 Ω) for maximum output level of 2.5 VPP. This gives a minimum voltage level at TXOUT of 1.2 VPP, corresponding to about 0 dBm at the coaxial cable. A 1-μF capacitor should be connected between the BIAS pin and GND. To obtain a nominal power level of 3 dBm at the feeder cable as the AISG standard requires, use R1 = 4.1 kΩ and R2 = 10 kΩ that provide 1.78 VPP at TXOUT.
In many applications the mast-top modem that receives data from the base distributes the received data through an RS-485 network to several mast-top devices. When the mast-top modem receives the first logic 0 bit (active modulated signal) it takes control of the mast-top RS-485 network by asserting the direction control signal. The duration of the direction control assertion should be optimized to pass a complete message of length B bits at the known signaling rate (1/tBIT) before relinquishing control of the mast-top RS-485 network. For example, if the messages are 10 bits in length (B=10) and the signaling rate is 9600 bits per second (tBIT = 0.104 ms) then a positive pulse of duration 1.7 ms is sufficient (with margin to allow for network propagation delays) to enable the mast-top RS-485 drivers to distribute each received message. Figure 23 shows the assertion of direction control.
The time constant for the direction control function can be set by the control mode pins, DIRSET1 and DIRSET2. These pins should be set to correspond to the desired data rate. With no external connections to the control mode pins, the internal time constant is set to the maximum value, corresponding to the minimum data rate.
Table 3 shows conversions between dBm and peak-to-peak voltage with a 50-Ω load, for various levels of interest including reference levels from the 3GPP TS 25.461 Technical Specification.
SIGNAL ON COAX | dBm | VPP |
---|---|---|
Maximum Driver ON Signal | 5 | 1.12 |
Nominal Driver ON Signal | 3 | 0.89 |
Minimum Driver ON Signal | 1 | 0.71 |
AISG Maximum Receiver Threshold | –12 | 0.16 |
Nominal Receiver Threshold | –15 | 0.11 |
Minimum Receiver Threshold | –18 | 0.08 |
Maximum Driver OFF Signal | –40 | 0.006 |
The AISG On-Off Keying (OOK) interface allows for command, control, and diagnostic information to be communicated between a base station and the corresponding tower-mounted antennae. Figure 24 shows a typical application.
An AISG transceiver is used to convert between digital logic-level signals and RF signals. The AISG standard requires an RF carrier frequency of 2.176 MHz with 100-ppm accuracy. The output signal of the driver, when active, should be from 1 dBm to 5 dBm. The receiver must be designed such that the input threshold is from –18 dBm to –12 dBm.
To ensure accuracy of the carrier frequency, an input reference frequency equal to four times the carrier (that is, 8.704 MHz) should be connected to the XTAL1 or XTAL2 inputs. This signal can come from a crystal (connected between XTAL1 and XTAL2) or from a PLL/clock generator circuit (connected to XTAL1 with XTAL2 grounded). The frequency accuracy must be within 100 ppm.
The driver output power level of the SN65HVD63 device can be adjusted through use of the RES pin. To align with AISG requirements, a nominal power level of 3 dBm should be configured by connecting a 4.1-kΩ resistor between RES and BIAS and a 10-kΩ resistor between RES and GND. Figure 25 shows an example schematic.
Figure 26 shows the application curve for the SN65HVD63 device.
The SN65HVD63 device has two power supply pins: VCC, which provides power to the analog circuitry, and VL, which is a logic supply. VCC should be operated from 3 V to 5.5 V, while VL can range from 1.6 V to 5.5 V to interface to different logic levels. Power supply decoupling capacitances of at least 0.1 µF should be placed as close as possible to each power supply pin.
Best practices for high-speed PCB design should be observed because the coax interface to the SN65HVD63 device operates at RF. The RF signaling traces should have a controlled characteristic impedance that is well-matched to the coaxial line. A continuous reference plane should be used to avoid impedance discontinuities. Power and ground distribution should be done through planes rather than traces to decrease series resistance and increase the effective decoupling capacitance on the power rails.
Control Interface for Antenna Line Devices, Antenna Interface Standards Group, Standard No. AISG v2.0
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