TLC5971 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver With 3.3-V Linear Regulator

8.3.1 Auto Display Repeat Function

This function repeats the total display period without a BLANK bit change, as long as the GS reference clock is available. This function can be enabled or disabled with DSPRPT (bit 214) in the data latch. When the DSPRPT bit is 1, this function is enabled and the entire display period repeats without a BLANK bit data change. When the DSPRPT bit is 0, this function is disabled and the entire display period executes only once after the BLANK bit is set to 0 or the internal latch pulse is generated when the display timing reset function is enabled. Figure 23 shows the auto display repeat operation timing.

Figure 23. Auto Repeat Display Function

8.3.2 Display Timing Reset Function

This function allows the display timing to be initialized using the internal latch pulse, as shown in Figure 24. This function can be enabled or disabled by TMGRST (bit 215) in the data latch. When the TMGRST bit is 1, the GS counter is reset to 0 and all outputs are forced off when the internal latch pulse is generated. This function is the same when the BLANK bit changes (such as from 0 to 1 and from 1 to 0). Therefore, the BLANK bit does not need to be controlled from an external controller to restart the PWM control from the next GS reference clock rising edge. When this bit is 0, the GS counter is not reset and no output is forced off even if the internal latch pulse is generated. Figure 24 shows the display timing reset operation.

Figure 24. Display Timing Reset Function

8.3.3 Output Timing Select Function

This function selects the ON-OFF change timing of the constant-current outputs (OUTXn) set by OUTTMG (bit 217) in the data latch. When this bit is 1, OUTXn are turned on or off at the rising edge of the selected GS reference clock. When this bit is 0, OUTXn are turned on or off at the falling edge of the selected clock. Electromagnetic interference (EMI) of the total system can be reduced using this bit setting. For example, when the odd number of devices in the system have this bit set to 0 and the even number of devices in the system have this bit set to 1, EMI is reduced because the devices change the OUTXn status at a deferent timing. Figure 25 and Figure 26 show the output switching timing when the OUTTMG bit is 1 and 0, respectively.

Figure 25. Output ON-OFF Timing With Four-Channel Grouped Delay (OUTTMG = 1)

Figure 26. Output ON-OFF Timing With Four-Channel Grouped Delay (OUTTMG = 0)

8.3.4 Thermal Shutdown

The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (T_J) exceeds the threshold (T_TSD = 165°C, typical). When the junction temperature drops below (T_TSD – T_HYS), the output control starts at the first GS clock in the next display period.

8.3.5 Noise Reduction

Large surge currents may flow through the IC and the board if all 12 outputs turn on simultaneously at the start of each GS cycle. These large current surges could induce detrimental noise and EMI into other circuits. The TLC5971 turns on the outputs for each color group independently with a 25 ns (typical) rise time. The output current sinks are grouped into three groups. The first group that is turned on/off are OUTR0-3; the second group that is turned on/off are OUTG0-3; and the third group is OUTB0-3. However, the state of each output is controlled by the selected GS clock; see the Output Timing Select Function section.

8.4.1 Maximum Constant Sink Current Setting

The maximum constant sink current value for each channel, I_OLCMax, is programmed through a single resistor, R_IREF, placed between IREF and GND. The desired value can be calculated with Equation 6:

Equation 6.

where

I_OLCMax is the maximum current for each output. Each output sinks the I_OLCMax current when it is turned on and global brightness control data (BC) are set to the maximum value of 7Fh (127d).

R_IREF must be between 0.82 kΩ and 24.8 kΩ to hold I_OLCMax between 60 mA (typical) and 2 mA (typical). Otherwise, the output may be unstable. Output currents lower than 2 mA can be achieved by setting I_OLCMax to 2 mA or higher and then using global brightness control to lower the output current. The constant-current sink values for specific external resistor values are shown in Figure 5 and Table 1.

8.5.1 Global Brightness Control (BC) Function (Sink Current Control)

The TLC5971 has the capability to adjust all output currents of each color group (OUTR0-3, OUTG0-3, and OUTB0-3) to the same current value. This function is called global brightness (BC) control. The BC data are seven bits long, which allows each color group output current to be adjusted in 128 steps from 0% to 100% of the maximum output current, I_OLCMax. The BC data are set through the serial interface. When the BC data are changed, the output current is changed immediately.

When the IC is powered on, all outputs are forced off by BLANK (bit 213). BLANK initializes in the data latch but the data in the 224-bit shift register and the 218-bit data latch are not set to a default value, except for the BLANK bit. Therefore, BC data must be written to the data latch when BLANK is set to 0.

Equation 7 determines each color group maximum output sink current:

Equation 7.

where

Table 2 summarizes the BC data value versus the output current ratio and set current value.

8.5.2 Grayscale (GS) Function (PWM Control)

The TLC5971 can adjust the brightness of each output channel using the enhanced spectrum pulse width modulation (ES-PWM) control scheme. The PWM bit length for each output is 16 bits. The use of the 16-bit length results in 65536 brightness steps from 0% to 100% brightness.

The PWM operation for all color groups is controlled by a 16-bit grayscale (GS) counter. The GS counter increments on each rising or falling edge of the external or internal GS reference clock that is selected by OUTTMG (bit 217) and EXTGCK (bit 216) in the data latch. When the external GS clock is selected, the GS counter uses the SCKI clock as the grayscale clock. The GS counter is reset to 0000h and all outputs are forced off when BLANK (bit 213) is set to 1 in the data latch and the counter value is held at 0 while BLANK is 1, even if the GS reference clock is toggled in between.

Equation 8 calculates each output (OUTXn) total on-time (t_{OUT_ON}):

Equation 8.

where

Table 3 summarizes the GS data values versus the output total ON-time and duty cycle. When the IC is powered up, BLANK (bit 213) is set to 1 to force all outputs off; however, the 224-bit shift register and the 218-bit data latch are not set to default values. Therefore, the GS data must be written to the data latch when BLANK (bit 213) is set to 0.

8.5.3 Enhanced Spectrum (ES) PWM Control

Enhanced spectrum (ES) PWM has the total display period divided into 128 display segments. The total display period refers the period between the first grayscale clock input to the 65536th grayscale clock input after BLANK (bit 213) is set to 0. Each display period has 512 grayscale values, maximum. Each output on-time changes depending on the grayscale data. Refer to Table 4 for sequence information and Figure 27 for timing information.

Figure 27. ES-PWM Operation

8.5.4 Register and Data Latch Configuration

The TLC5971 has a 224-bit shift register and a 218-bit data latch that set grayscale (GS) data, global brightness control (BC), and function control (FC) data into the device. When the internal latch pulse is generated and the data of the six MSBs in the shift register are 25h, the 218 following data bits in the shift register are copied into the 218-bit data latch. If the data of the six MSBs is not 25h, the 218 data bits are not copied into the 218-bit data latch. The data in the data latch are used for GS, BC, and FC functions. Figure 28 shows the shift register and the data latch configuration.

Figure 28. Common Shift Register and Control Data Latch Configuration

8.5.4.2 218-Bit Data Latch

The 218-bit data latch is used to latch the GS, BC, and FC data. The 218 LSBs in the 244-bit shift register are copied to the data latch when the internal latch pulse is generated with the 6-bit write command, 25h (100101b). When the device is powered up, the data in the latch are not reset except for BLANK (bit 213) which is set to 1 to force all outputs off. Therefore, GS, BC, and FC data must be set to the proper values before BLANK is set to 0. The 218-bit data latch configuration is shown in Figure 29 and the data bit assignment is shown in Table 5.

Figure 29. 218-Bit Data Latch Configuration

Table 5. Data Latch Bit Assignment

BIT NUMBER	BIT NAME	CONTROLLED CHANNEL/FUNCTIONS
15-0	GSR0	GS data bits 15 to 0 for OUTR0
31-16	GSG0	GS data bits 15 to 0 for OUTG0
47-32	GSB0	GS data bits 15 to 0 for OUTB0
63-48	GSR1	GS data bits 15 to 0 for OUTR1
79-64	GSG1	GS data bits 15 to 0 for OUTG1
95-80	GSB1	GS data bits 15 to 0 for OUTB1
111-96	GSR2	GS data bits 15 to 0 for OUTR2
127-112	GSG2	GS data bits 15 to 0 for OUTG2
143-128	GSB2	GS data bits 15 to 0 for OUTB2
159-144	GSR3	GS data bits 15 to 0 for OUTR3
175-160	GSG3	GS data bits 15 to 0 for OUTG3
191-176	GSB3	GS data bits 15 to 0 for OUTB3
198-192	BCR	BC data bits 6 to 0 for OUTR0-3
205-199	BCG	BC data bits 6 to 0 for OUTG0-3
212-206	BCB	BC data bits 6 to 0 for OUTB0-3
213	BLANK	Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). When this bit is 0, all constant-current outputs (OUTR0-OUTB3) are controlled by the GS PWM timing controller. When this bit is 1, all constant-current outputs are forced off. The GS counter is reset to 0, and the GS PWM timing controller is initialized. When the IC is powered on, this bit is set to 1.
214	DSPRPT	Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled). When this bit is 0, the auto repeat function is disabled. Each constant-current output is only turned on once, according the GS data after BLANK is set to 0 or after the internal latch pulse is generated with the TMGRST bit set to 1. When this bit is 1, each output turns on and off according to the GS data every 65536 GS reference clocks.
215	TMGRST	Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled). When this bit is 1, the GS counter is reset to 0 and all constant-current outputs are forced off when the internal latch pulse is generated for data latching. This function is the same when BLANK is set to 0. Therefore, BLANK does not need to be controlled by an external controller when this mode is enabled. When this bit is 0, the GS counter is not reset and no output is forced off even if the internal latch pulse is generated.
216	EXTGCK	GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock). When this bit is 1, PWM timing refers to the SCKI clock. When this bit is 0, PWM timing refers to the internal oscillator clock.
217	OUTTMG	GS reference clock edge select bit for OUTXn on-off timing control in FC data (0 = falling edge, 1 = rising edge). When this bit is 1, OUTXn are turned on or off at the rising edge of the selected GS reference clock. When this bit is 0, OUTXn are turned on or off at the falling edge of the selected clock.

8.5.5 Internal Latch Pulse Generation Timing

The internal latch pulse is generated when the SCKI rising edge does not change for 8x the period between the last SCKI rising edge and the second to last SCKI rising edge if the data of the six MSBs in the 244-bit shift register are the command code 25h. The generation timing changes as a result of the SCKI frequency with the time range between 16384 times the internal oscillator period (2.74 ms), maximum, and 8x the internal oscillator period (666 ns), minimum. Figure 30 shows the internal latch pulse generation timing.

Figure 30. Data Latch Pulse Generation Timing

9.2.1 Design Requirements

For this design example, use Table 6 as the input parameters.

9.2.2 Detailed Design Procedure

9.2.2.3 How to Control the TLC5971

To set each function mode, BC color, GS output, 6-bit write command, 5-bit FC data, 21-bit BC data for each color group, and 192-bit GS data for OUTXn, a total number of 224 bits must be written into the device. Figure 32 shows the 224-bit data packet configuration.

When N units of the TLC5971 are cascaded (as shown in Figure 33), N × 224 bits must be written from the controller into the first device to control all devices. The number of cascaded devices is not limited as long as the proper voltage is supplied to the device at VCC. The packets for all devices must be written again whenever the data in one packet is changed.

Figure 32. 224-Bit Data Packet Configuration

Figure 33. Cascading Connection of N TLC5971 Units

9.2.2.3.1 Data Write and PWM Control with Internal Grayscale Clock Mode

When the EXTCLK bit is 0, the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for illumination applications that change the display image at low frequencies. The data and clock timing is shown in Figure 3 and Figure 34. A writing procedure for the function setting and display control follows:

1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC5971 using the SDTI and SCKI signals. The first six bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK bit must be set to 0 for the internal oscillator mode. Also, the DSPRPT bit should be set to 1 to repeat the PWM timing control and BLANK set to 0 to start the PWM control.
3. Write the 224-bit data packet for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is now 224 × N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.

Figure 34. Data Packet and Display Start/Update Timing 1 (Internal Oscillator Mode)

9.2.2.3.2 Data Write and PWM Control with External Grayscale Clock Mode

When the EXTCLK bit is 1, the data shift clock (SCKI) is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for video image applications that change the display image with high frequencies or for certain display applications that must synchronize all TLC5971s. The data and clock timing are shown in Figure 3 and Figure 35. A writing procedure for the display data and display timing control follows:

1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet MSB-first for the Nth TLC5971 using the SDTI and SCKI signals. The first six bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that the PWM control is not repeated, the TMGRST bit should be set to 1 to reset the PWM control timing at the internal latch pulse generation, and BLANK must be set to 0 to start the PWM control.
3. Write the 224-bit data for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is 224 × N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
5. To start the PWM control, send one pulse of the SCKI clock with SDTI low after 1.34 µs or more from step 4. The OUTXn are turned on when the output GS data are not 0000h.
6. Send the remaining 65535 SCKI clocks with SDTI low. Then the PWM control for OUTXn is synchronized with the SCKI clock and one display period is finished with a total of 65536 SCKI clock periods.
7. Repeat step 2 to step 6 for the next display period.

Figure 35. Data Packet and Display Start/Update Timing 2 (External Clock Mode)

There is another control procedure that is recommended for a long chain of cascaded devices. The data and clock timings are shown in Figure 3 and Figure 36. When 256 TLC5971 units are cascaded, use the following procedure:

1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet MSB-first for the 256th TLC5971 using the SDTI and SCKI signals. The EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that the PWM control does not repeat, the TMGRST bit should be set to 1 to reset the PWM control timing with the internal latch pulse, and BLANK must be set to 0 to start the PWM control.
3. Repeat the data write sequence for all TLC5971s. The total shift clock count (SCKI) is 57344 (224 × 256). After all device data are written, stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34 µs or more from step 3 (or step 7). These 8192 clock periods are used for the OUTXn PWM control.
5. Write the new 224-bit data packets to the 256th to first TLC5971s for the next display with 256 × 224 SCKI clock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock and one display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used for PWM control and, at the same time, to write data into the shift registers of all cascaded parts.
6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
7. Repeat step 4 to step 6 for the next display periods.

Figure 36. Data Packet and Display Start/Update Timing 3
(External Clock Mode With 256 Cascaded Devices)

9.2.3 Application Curve

Figure 37. Output Waveform With GS Data Latch Input