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Interfacing the TI AFE7769DEVM With the Altera Arria 10 FPGA
SBAU484
February 2025
AFE7728D
,
AFE7768D
,
AFE7769D
CONTENTS
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Interfacing the TI AFE7769DEVM With the Altera Arria 10 FPGA
1
Abstract
Trademarks
1
Introduction
2
Hardware and Software Setup
2.1
Hardware Setup
2.2
Software Setup
2.3
Test Cases
2.3.1
Initial Bringup for All Test Cases
2.3.1.1
Test Case 1: Generate Sinusoidal tx_data From NCO @ 5MHz
2.3.1.2
Test case 2: Generate Sinusoidal tx_data From NCO @ 20MHz
2.3.1.3
Test Case 3: Connect Signal Generator Output Port to RX of the AFE7769DEVM (at output power, -13dBm)
2.3.1.4
Test Case 4: Connect Signal Generator Output Port to RX of the AFE7769DEVM (at output power, -23dBm)
IMPORTANT NOTICE
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Interfacing the TI AFE7769DEVM With the Altera Arria 10 FPGA