TPS7A39 Dual, 150-mA, Wide VIN Positive and Negative LDO Voltage Regulator
- SBVS263A July 2017 – September 2017 TPS7A39
  
  PRODUCTION DATA.

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DATA SHEET

TPS7A39 Dual, 150-mA, Wide VIN Positive and Negative LDO Voltage Regulator

1 Features

Positive and Negative LDOs in One Package
Wide Input Voltage Range: ±3.3 V to ±33 V
Wide Output Voltage Range:
- Positive Range: 1.2 V to 30 V
- Negative Range: –30 V to 0 V
Output Current: 150 mA per Channel
Monotonic Start-Up Tracking
High Power-Supply Rejection Ratio (PSRR):
- 69 dB (120 Hz)
- ≥ 50 dB (10 Hz to 2 MHz)
Output Voltage Noise: 21 µV_RMS (10 Hz–100 kHz)
Buffered 1.2-V Reference Output
Stable With a 10-µF or Larger Output Capacitor
Single Positive-Logic Enable
Adjustable Soft-Start In-Rush Control
3-mm × 3-mm, 10-Pin WSON Package
Low Thermal Resistance: R_θJA = 44.4°C/W
Operating Temperature Range: –40 to +125°C

2 Applications

Supply Rails for Op Amps, ADCs, DACs, and Other High-Precision Analog Circuitry
Post DC-DC Regulation and Filtering
Analog I/O Modules
Test and Measurement
Rx, Tx, and PA Circuitry
Industrial Instrumentation
Medical Imaging

3 Description

The TPS7A39 device is a dual, monolithic, high-PSRR, positive and negative low-dropout (LDO) voltage regulator capable of sourcing (and sinking) up to 150 mA of current. The regulated outputs can be independently and externally adjusted to symmetrical or asymmetrical voltages, making this device an ideal dual, bipolar power supply for signal conditioning.

Both positive and negative outputs of the TPS7A39 ratiometrically track each other during startup to mitigate floating conditions and other power-supply sequencing issues common in dual-rail systems. The negative output can regulate up to 0 V, extending the common-mode range for single-supply amplifiers. The TPS7A39 also features high PSRR to eliminate power-supply noise, such as switching noise, that can compromise signal integrity.

Both regulators are controlled with a single positive logic enable pin for interfacing with standard digital logic. A capacitor-programmable soft-start function controls in-rush current and start-up time. The internal reference voltage of the TPS7A39 can be overridden with an external reference to enable precision outputs, output voltage margining, or to track other power supplies. Additionally, the TPS7A39 has a buffered reference output that can be used as a voltage reference for other components in the system.

These features make the TPS7A39 a robust, simplified solution to power operational amplifiers, digital-to-analog converters (DACs), and other precision analog circuitry.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS7A39	WSON (10)	3.00 mm × 3.00 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Powering the Signal Chain

Monotonic Start-Up Tracking

4 Revision History

Changes from * Revision (July 2017) to A Revision

Released to production Go

5 Pin Configuration and Functions

DSC Package

10-Pin WSON

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	INP	I	Positive input. A 10-μF⁽¹⁾ or larger capacitor must be tied from this pin to ground to ensure stability. Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section for more information.
2	EN	I	Enable pin. Driving this pin to logic high (V_EN ≥ V_IH(EN)) enables the device; driving this pin to logic low (V_EN ≤ V_IL(EN)) disables the device. If enable functionality is not required, this pin must be connected to INP; see the Application and Implementation section for more detail. The enable voltage cannot exceed the input voltage (V_EN ≤ V_INP).
3	NR/SS	—	Noise-reduction, soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and enables soft-start and start-up tracking. A 10-nF or larger capacitor (C_NR/SS) is recommended to be connected from NR/SS to GND to maximize or optimize ac performance and to ensure start-up tracking. This pin can also be driven externally to provide greater output voltage accuracy and lower noise, see the User-Settable Buffered Reference section for more information.
4	GND	—	Ground pin. This pin must be connected to ground and the thermal pad with a low-impedance connection.
5	INN	I	Negative input. A 10-μF⁽¹⁾ or larger capacitor must be tied from this pin to ground to ensure stability. Place the input capacitor as close to the input as possible; see the Capacitor Recommendations section for more information.
6	OUTN	O	Negative output. A 10-μF⁽¹⁾ or larger capacitor must be tied from this pin to ground to ensure stability. Place the output capacitor as close to the output as possible; see the Capacitor Recommendations section for more information.
7	FBN	I	Negative output feedback pin. This pin is used to set the negative output voltage. Although not required, a 10-nF feed-forward capacitor from FBN to OUTN (as close to the device as possible) is recommended to maximize ac performance. Nominally this pin is regulated to V_FBN. Do not connect to ground.
8	BUF	O	Buffered reference output. This pin is connected to FBN through R₂ and the voltage at this node is inverted and scaled up by the negative feedback network to provide the desired output voltage. The buffered reference can be used to drive external circuits, and has a 1-mA maximum load.
9	FBP	I	Positive output feedback pin. This pin is used to set the positive output voltage. Although not required, a 10-nF feed-forward capacitor from FBP to OUTP (as close to the device as possible) is recommended to maximize ac performance. Nominally this pin is regulated to V_FBP. Do not connect this pin directly to ground.
10	OUTP	O	Positive output. A 10-μF⁽¹⁾ or larger capacitor must be tied from this pin to ground to ensure stability. Place the output capacitor as close to the output as possible; see the Capacitor Recommendations section for more information.
Pad	Thermal Pad	—	Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.

(1) The nominal input and output capacitance must be greater than 2.2 µF; throughout this document the nominal derating on these capacitors is 80%. Take care to ensure that the effective capacitance at the pin is greater than 2.2 µF.

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Voltage	INP	–0.3	36	V
	INN	–36	0.3
	OUTP	–0.3	V_INP + 0.3⁽⁵⁾
	OUTN	V_INN – 0.3⁽⁴⁾	0.3
	FBP	–0.3	V_INP + 0.3⁽⁷⁾
	BUF	–1	V_INP + 0.3⁽⁷⁾
	NR/SS	–0.3	V_INP + 0.3⁽⁸⁾
	FBN	V_INN – 0.3⁽³⁾	0.3
	EN	–0.3	V_INP + 0.3⁽⁶⁾
Current	Output current	Internally limited
Current	Buffer current		2	mA
Temperature	Operating junction temperature, T_J	–55	150	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages with respect to the ground pin, unless otherwise noted.

(3) The absolute maximum rating is V_INN – 0.3 V or –3 V, whichever is greater.

(4) The absolute maximum rating is V_INN – 0.3 V or –33 V, whichever is greater.

(5) The absolute maximum rating is V_INP + 0.3 V or 33 V, whichever is smaller.

(6) The absolute maximum rating is V_INP + 0.3 V or 36 V, whichever is smaller.

(7) The absolute maximum rating is V_INP + 0.3 V or 3 V, whichever is smaller.

(8) The absolute maximum rating is V_INP + 0.3 V or 2 V, whichever is smaller.

6.2 ESD Ratings

			VALUE	UNIT
V_ESD	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_ESD	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
\|V_INx\|	Supply voltage magnitude for either regulator	3.3		33	V
V_EN	Enable supply voltage	0		V_INP	V
V_OUTP	Positive regulated output voltage range	V_FBP		30	V
V_OUTN	Negative regulated output voltage range	–30		V_FBN	V
I_OUTx	Output current for either regulator	0.005⁽²⁾		150	mA
I_BUF	Output current from the BUF pin	0	120	1000	µA
C_INx	Input capacitor for either regulator	4.7	10⁽¹⁾		µF
C_OUTx	Output capacitor for either regulator	4.7	10⁽¹⁾		µF
C_NR/SS	Noise-reduction and soft-start capacitor	0⁽³⁾	10	1000	nF
C_FFP	Positive channel feed-forward capacitor; connect from V_OUTP to FBP	0	10	100	nF
C_FFN	Negative channel feed-forward capacitor; connect from V_OUTN to FBN	0	10	100	nF
R_2P	Lower positive feedback resistor		10	240	kΩ
R_2N	Lower negative feedback resistor (from FBN to BUF)		10	240	kΩ
T_J	Operating junction temperature	–40		125	°C

(1) The nominal input and output capacitor value of 10-µF accounts for the derating factors that apply to X5R and X7R ceramic capacitors. The assumed overall derating is 80%.

(2) Minimum load required when feedback resistors are not used. If feedback resistors are used, keeping R_2x below 240 kΩ satisfies this requirement.

(3) For startup tracking to function correctly a minimum 4.7-nF C_NR/SS capacitor must be used.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7A39	UNIT
		DSC (WSON)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	44.4	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	33.7	°C/W
R_θJB	Junction-to-board thermal resistance	19.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	19.5	°C/W
R_θJC(bot)	Junction-to-case(bottom) thermal resistance	2.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at T_J= –40°C to +125°C, V_INP(nom) = V_OUTP(nom) + 1 V or V_IN(nom) = 3.3 V (whichever is greater), V_INN(nom) = V_OUTN(nom) – 1 V or V_INN(nom) = –3.3 V (whichever is less), V_EN = V_INP, I_OUT = 1 mA, C_INx = 2.2 μF, C_OUTx = 10 μF, C_FFx = C_NR/SS = open, R_1N = R_2N = 10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at T_J = 25°C

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_INP	Input voltage range, positive channel			3.3		33	V
V_INN	Input voltage range, negative channel			–33		–3.3	V
V_{UVLOP(rising)}	Undervoltage lockout threshold, positive channel		V_INP rising, V_INN = –3.3 V	1.4		3.1	V
V_UVLOP(hys)	Undervoltage lockout threshold, positive channel hysteresis		V_INP falling, V_INN = –3.3 V		120		mV
V_{UVLON(falling)}	Undervoltage lockout threshold, negative channel		V_INN falling, V_INP = 3.3 V	–3.1		–1.4	V
V_UVLON(hys)	Undervoltage lockout threshold, negative channel, hysteresis		V_INN rising, V_INP = 3.3 V		70		mV
V_NR/SS	Internal reference voltage			1.172	1.19	1.208	V
V_FBP	Positive feedback voltage			1.170	1.188	1.206	V
V_FBN	Negative feedback voltage			–10	3.7	10	mV
V_OUT	Output voltage range⁽²⁾	Positive channel		V_FBP		30	V
	Output voltage range⁽²⁾	Negative channel		–30		V_FBN⁽¹⁾	V
	V_OUTP accuracy		V_INP(nom) ≤ V_INP ≤ 33 V, 1 mA ≤ I_OUTP ≤ 150 mA, 1.2 V ≤ V_OUTP(nom) ≤ 30 V	–1.5		1.5	%V_OUT
	V_OUTN accuracy⁽³⁾		–33 V ≤ V_INN ≤ V_INN(nom), –150 mA ≤ I_OUTN ≤ –1 mA, –30 V ≤ V_OUTN(nom) ≤ –1.2 V	–3		3	%V_OUT
	Negative V_OUT channel accuracy		–33 V ≤ V_INN ≤ V_INN(nom) , –150 mA ≤ I_OUTN ≤ 1 mA, –1.2 V < V_OUTN(nom) < 0 V	–36		36	mV
	Negative V_OUT channel accuracy		–33 V ≤ V_INN ≤ V_INN(nom) , –150 mA ≤ I_OUTN ≤ 1 mA, V_OUTN(nom) = 0 V	–12		12	mV
ΔV_OUT(ΔV_IN) / V_OUT(NOM)	Line regulation, positive channel		V_INP(nom) ≤ V_INP ≤ 33 V		0.035		%V_OUT
ΔV_OUT(ΔV_IN) / V_OUT(NOM)	Line regulation, negative channel		–33 V ≤ V_INN ≤ V_OUT(nom) + 1 V		0.125		%V_OUT
ΔV_OUT(ΔI_OUT) / V_OUT(NOM)	Load regulation, positive channel		1 mA ≤ I_OUTP ≤ 150 mA		–0.09		%V_OUT
ΔV_OUT(ΔI_OUT) / V_OUT(NOM)	Load regulation, negative channel		–150 mA ≤ I_OUTN ≤ –1 mA		0.715		%V_OUT
V_DO	Dropout voltage	Positive channel	I_OUTP = 50 mA, 3.3 V ≤ V_INP(nom)≤ 33.0 V, V_FBP = 1.070 V		175	300	mV
		Positive channel	I_OUTP = 150 mA, 3.3 V ≤ V_INP(nom)≤ 33.0 V, V_FBP = 1.070 V		300	500
		Negative channel	I_OUTN = –50 mA, –3.3 V ≤ V_INN(nom)≤ –33.0 V, V_FBN = 0.0695 V	–250	–145
		Negative channel	I_OUTN = –150 mA, –3.3 V ≤ V_INN(nom)≤ –33.0 V, V_FBN = 0.0695 V	–400	–275
V_BUF	Buffered reference output voltage				V_NR/SS		V
V_BUF/I_BUF	Buffered reference load regulation		I_BUF = 100 µA to 1 mA		1		mV/mA
V_BUF – V_NR/SS	Output buffer offset voltage		V_NR/SS = 0.25 V to 1.2 V	–4	3	8	mV
V_OUTP–V_OUTN	DC output voltage difference with a forced REF voltage		V_NR/SS = 0.25 V to 1.2 V	–10		10	%V_NR/SS
I_LIM	Current limit	Positive channel	V_OUTP = 90% V_OUTP(nom)	200	330	500	mA
I_LIM	Current limit	Negative channel	V_OUTN = 90% V_OUTN(nom)	–500	–300	–200	mA
I_SUPPLY	Supply current	Positive channel	I_OUTP = 0 mA, R_2N = open, V_INP = 33 V		75	150	µA
		Positive channel	I_OUTP = 150 mA, R_2N = open, V_INP = 33 V		904
		Negative channel	I_OUTN = 0 mA, V_OUTN(nom)= 0 V, R_2N = open, V_INN = –33 V	–150	–60
		Negative channel	I_OUTN = 150 mA, R_2N = open, V_INN = –33 V		–1053
I_SHDN	Shutdown supply current	Positive channel	V_EN = 0.4 V, V_INP = 33 V		3.75	6.5	µA
I_SHDN	Shutdown supply current	Negative channel	V_EN = 0.4 V, V_INN = –33 V	–4.5	–2.25		µA
I_FBx	Feedback pin leakage current	Positive channel			5.5	100	nA
I_FBx	Feedback pin leakage current	Negative channel		–100	–9.7		nA
I_NR/SS	Soft-start charging current		V_NR/SS = 0.9 V	3	5.1	6.7	µA
I_EN	Enable pin leakage current		V_EN = V_INP = 33 V		0.02	1	µA
V_IH(EN)	Enable high-level voltage			2.2		V_INP	V
V_IL(EN)	Enable low-level voltage			0		0.4	V
PSRR	Power-supply rejection ratio		\|V_IN\| = 6 V, \|V_OUT(nom)\| = 5 V, C_OUT = 10 μF, C_NR/SS = C_FF= 10 nF, f = 120 Hz		69		dB
V_n	Output noise voltage	Positive channel	V_INP = 3.3 V, V_OUTP(nom) = V_NR/SS, C_OUTP = 10 μF, C_NR/SS = 10 nF, BW = 10 Hz to 100 kHz		20.63		µV_RMS
		Positive channel	V_INP = 6 V, V_OUTP(nom) = 5 V, C_OUTP = 10 μF, C_NR/SS = C_FF = 10 nF, BW = 10 Hz to 100 kHz		26.86
		Negative channel	V_INN = –3 V, V_OUTN(nom) = –V_NR/SS, C_OUTP = 10 μF, C_NR/SS = 10 nF, BW = 10 Hz to 100 kHz		22.13
		Negative channel	V_INN = –6 V, V_OUTN(nom) = –5 V, C_OUTP = 10 μF, C_NR/SS = C_FF= 10 nF, BW = 10 Hz to 100 kHz		28.68
R_NR/SS	Filter resistor from band gap to NR pin				350		kΩ
T_sd	Thermal shutdown temperature		Shutdown, temperature increasing		175		°C
T_sd	Thermal shutdown temperature		Reset, temperature decreasing		160		°C

(1) V_OUT(target) = 0 V, R_1N = 10 kΩ, R_2N = open.

(2) To ensure V_OUT does not drift up while the device is disabled, a minimum load current of 5 µA is required.

(3) The device is not tested under conditions where the power dissipated across the device, P_D, exceeds 2 W.

6.6 Startup Characteristics

at T_J= –40°C to +125°C, V_INP(nom) = V_OUTP(nom) + 1 V or V_IN(nom) = 3.3 V (whichever is greater), V_INN(nom) = V_OUTN(nom) – 1 V or V_INN(nom) = –3.3 V (whichever is less), V_EN = V_INP, I_OUT = 1 mA, C_INx = 2.2 μF, C_OUTx = 10 μF, C_FFx = C_NR/SS = 4.7nF, R_1N = R_2N = 10 kΩ, and FBP tied to OUTP (unless otherwise noted); typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_EN(delay)	Delay time from EN low-to-high transition to 2.5% V_OUTP	From EN low-to-high transition to V_OUTP = 2.5% × V_OUTP(nom)		300		µs
t_start-up	Delay time from EN low-to-high transition to both outputs reaching 95% of final value	From EN low-to-high transition to V_OUTP = V_OUTP(nom) × 95% and V_OUTN = V_OUTN(nom) × 95%		1.1		ms
t_{Pstart-Nstart}	Delay time from V_OUTP leaving a high-impedance state to V_OUTN leaving a high-impedance state	From V_OUTP = V_OUTP(nom) × 2.5% to V_OUTN = V_OUTN(nom) × 2.5%	–40	–17	40	µs
Δ\|V_OUTP – V_OUTN\|	Voltage difference between the positive and negative output	During t_{Pstart-Nstart}		75	300	mV

NOTE:

Slow ramps (t_rise(VINx) > 10 ms typically) on V_INx with EN tied to V_INP does not meet the tracking specification. Use a resistor divider from V_INP to EN for these applications.

Figure 1. Start-Up Characteristics

6.7 Typical Characteristics

at T_J= 25°C, V_INP = V_OUTP(nom) + 1.0 V or V_IN = 3.3 V (whichever is greater), V_INN = V_OUTN(nom) – 1 V or –3.3 V (whichever is less), V_EN = V_IN, I_OUT = 1 mA, C_IN = 10-μF ceramic, C_OUT = 10-μF ceramic, and C_FFP = C_FFN = C_NR/SS = 10 nF (unless otherwise noted)

V_OUTP = 5 V, I_OUTP = 150 mA, V_OUTN = –5 V, I_OUTN = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 2. Positive PSRR vs Frequency and V_INP

V_OUTP = 5 V, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 4. Positive PSRR vs Frequency and I_OUTP

V_OUTP = 5 V, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 6. Positive PSRR vs Frequency and C_OUTP

V_OUTP = 5 V, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA, C_NR/SS = 10 nF

Figure 8. Positive PSRR vs Frequency and C_FFP

V_OUTP = 5 V, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA,
C_FFx = 10 nF

Figure 10. Positive PSRR vs Frequency and C_NR/SS

Figure 12. Crosstalk Positive to Negative

I_OUTP = 150 mA, V_INP = V_EN, V_OUTN = –V_OUTP, I_OUTN = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 14. Positive Spectral Noise Density vs Frequency and V_OUTP

V_OUTP = 5 V, I_OUTP = 150 mA, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA, C_FFx = 10 nF

Figure 16. Positive Spectral Noise Density vs Frequency and C_NR/SS

V_OUTP = 5 V, I_OUTP = 150 mA, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA, C_NR/SS = 10 nF

Figure 18. Positive Spectral Noise Density vs Frequency and C_FF

V_OUTP = 5 V, I_OUTP = 150 mA, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 20. Positive Spectral Noise Density vs Frequency and C_OUT

V_OUTP = 5 V, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTN = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 22. Positive Spectral Noise Density vs Frequency and I_OUT

V_OUTP = –V_OUTN = 5 V, V_INP = –V_INN = 12 V

Figure 24. Startup (V_INP = V_EN)

TPS7A39 tc_PosReg_LineTransient_1VperUs.gif

V_INP = 5.5 V to 10 V at 1 V/µs, V_OUTP = –V_OUTN = 5 V,
I_OUTN = 0 mA, I_OUTP = 150 mA

Figure 26. Line Transient Positive Regulator

TPS7A39 tc_PosReg_LineTransient_4VperUs.gif

V_INP = 5.5 V to 10 V at 4 V/µs, V_OUTP = –V_OUTN = 5 V,
I_OUTN = 0 mA, I_OUTP = 150 mA

Figure 28. Line Transient Positive Regulator

TPS7A39 tc_PosReg_LoadTransient_1AperUs.gif

V_INP = 6 V, V_OUTP = –V_OUTN = 5 V, I_OUTN = 0 mA,
I_OUTP = 1 mA to 150 mA at 1 A/µs

Figure 30. Load Transient Positive Regulator

V_OUTN = 0 V

Figure 32. Negative Line Regulation

V_OUTN = –1.19 V

Figure 34. Negative Line Regulation

V_OUTN = –24 V

Figure 36. Negative Line Regulation

V_OUTN = –15 V, V_INN = –16 V

Figure 38. Negative Load Regulation

V_OUTP = 1.188 V, V_INP = 3.3 V

Figure 40. Positive Load Regulation

V_OUTP = 30 V, V_INP = 33 V

Figure 42. Positive Load Regulation

V_OUTP = 15 V

Figure 44. Positive Line Regulation

V_OUTP = 1.188 V

Figure 46. Positive Regulator Current Limit

Figure 48. Positive Regulator Dropout Voltage vs
Input Voltage

V_INP = 3.3 V

Figure 50. Positive Regulator Dropout Voltage vs
Output Current

Figure 52. Enable Threshold vs Temperature

Figure 54. Positive Output Discharge Current vs
Output Voltage

TPS7A39 tc_SupplyCurrent_vs_outputCurrent_1p2V_PosReg.gif

V_OUTP = 1.188 V

Figure 56. Positive Supply Current vs Output Current

V_OUTN = –1.19 V

Figure 58. Buffer Accuracy vs Buffer Current

V_OUTP = 5 V, I_OUTP = 0 mA, V_OUTN = –5 V, I_OUTN = 150 mA, C_NR/SS = C_FFx = 10 nF

Figure 3. Negative PSRR vs Frequency and V_INN

V_OUTP = 5 V, I_OUTP = 0 mA, V_INN = –6 V, V_OUTN = –5 V,
C_NR/SS = C_FFx = 10 nF

Figure 5. Negative PSRR vs Frequency and I_OUTN

V_OUTP = 5 V, I_OUTP = 0 mA, V_INN = –6 V, V_OUTN = –5 V,
C_NR/SS = C_FFx = 10 nF, C_OUTP = 10 µF

Figure 7. Negative PSRR vs Frequency and C_OUTN

V_OUTP = 5 V, I_OUTP = 0 mA, V_INN = –6 V, V_OUTN = –5 V,
C_NR/SS = C_FFP = 10 nF

Figure 9. Negative PSRR vs Frequency and C_FFN

V_OUTP = 5 V, I_OUTP = 0 mA, V_INN = –6 V, V_OUTN = –5 V,
C_FFx = 10 nF

Figure 11. Negative PSRR vs Frequency and C_NR/SS

Figure 13. Crosstalk Negative to Positive

I_OUTN = –150 mA, V_INP = V_EN, V_OUTN = –V_OUTP, I_OUTP = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 15. Negative Spectral Noise Density vs Frequency and V_OUTN

V_OUTN = –5 V, I_OUTN = –150 mA, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTP = 0 mA, C_FFx = 10 nF

Figure 17. Negative Spectral Noise Density vs Frequency and C_NR/SS

V_OUTN = –5 V, I_OUTN = –150 mA, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTP = 0 mA, C_NR/SS = 10 nF

Figure 19. Negative Spectral Noise Density vs Frequency and C_FF

V_OUTN = –5 V, I_OUTN = –150 mA, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTP = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 21. Negative Spectral Noise Density vs Frequency and C_OUT

V_OUTN = –5 V, V_INP = V_EN = 6 V, V_OUTN = –5 V, I_OUTP = 0 mA, C_NR/SS = C_FFx = 10 nF

Figure 23. Negative Spectral Noise Density vs Frequency and I_OUT

V_OUTP = –V_OUTN = 5 V, V_INP = –V_INN = 15 V

Figure 25. Startup With EN

TPS7A39 tc_NegReg_LineTransient_1VperUs.gif

V_INN = –5.5 V to –10 V at 1 V/µs, V_OUTP = –V_OUTN = 5 V,
I_OUTN = –150 mA, I_OUTP = 0 mA

Figure 27. Line Transient Negative Regulator

TPS7A39 tc_NegReg_LineTransient_4VperUs.gif

V_INN = –5.5 V to –10 V at 4 V/µs, V_OUTP = –V_OUTN = 5 V,
I_OUTN = –150 mA, I_OUTP = 0 mA

Figure 29. Line Transient Negative Regulator

TPS7A39 tc_NegReg_LoadTransient_1AperUs.gif

V_INN = –6 V, V_OUTP = –V_OUTN = 5 V, I_OUTN = 0 mA,
I_OUTN = –1 mA to –150 mA at 1 A/µs

Figure 31. Load Transient Negative Regulator

V_OUTN = 0 V, V_INN = –3.3 V

Figure 33. Negative Load Regulation

V_OUTN = –15 V

Figure 35. Negative Line Regulation

V_OUTN = –1.2 V, V_INN = –3.3 V

Figure 37. Negative Load Regulation

V_OUTN = –30 V, V_INN = –33 V

Figure 39. Negative Load Regulation

V_OUTP = 15 V, V_INP = 16 V

Figure 41. Positive Load Regulation

V_OUTP = 1.188 V

Figure 43. Positive Line Regulation

V_OUTP = 24 V

Figure 45. Positive Line Regulation

V_OUTN = –1.19 V

Figure 47. Negative Regulator Current Limit

Figure 49. Negative Regulator Dropout Voltage vs
Input Voltage

V_OUTN = –3.3 V

Figure 51. Negative Regulator Dropout Voltage vs
Output Current

Figure 53. I_NR/SS vs V_NR/SS

Figure 55. Negative Output Discharge Current vs
Output Voltage

TPS7A39 tc_SupplyCurrent_vs_outputCurrent_n1p2V_NegReg.gif

V_OUTN = –1.19 V

Figure 57. Negative Supply Current vs Output Current