Loading [MathJax]/jax/output/SVG/fonts/TeX/fontdata.js
Menu
Product
Email
PDF
Order now
LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer
SNAS828A
february 2022 – june 2023
LMK1D1208I
PRODUCTION DATA
CONTENTS
SEARCH
LMK1D1208I I2C-Configurable, Low-Additive Jitter LVDS Buffer
1
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Fail-Safe Input
9.3.2
Input Stage Configurability
9.3.3
Dual Output Bank
9.3.4
I2C
9.3.4.1
I2C Address Assignment
9.3.5
LVDS Output Termination
9.3.6
Input Termination
9.4
Device Functional Modes
9.4.1
Input Enable Control
9.4.2
Bank Input Selection
9.4.3
Bank Mute Control
9.4.4
Output Enable Control
9.4.5
Output Amplitude Selection
9.5
Programming
9.6
Register Maps
9.6.1
LMK1D1208I Registers
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
10.3
Power Supply Recommendations
10.4
Layout
10.4.1
Layout Guidelines
10.4.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.2
Tape and Reel Information
IMPORTANT NOTICE
search
No matches found.
Full reading width
Full reading width
Comfortable reading width
Expanded reading width
Card for each section
Card with all content