SLUSDT9B May   2020  – March 2021 UCC23513-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Function
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Rise Time and Fall Time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Resistor
        2. 9.2.2.2 Gate Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
        5. 9.2.2.5 Selecting VCC Capacitor
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 qualified for automotive applications
  • 5.7-kVRMS single channel isolated gate driver with opto-compatible input
  • Pin-to-pin, drop in upgrade for opto isolated gate drivers
  • 4.5-A source / 5.3-A sink, peak output current
  • Maximum 33-V output driver supply voltage
  • 8-V (B) or 12-V VCC UVLO Options
  • Rail-to-rail output
  • 105-ns (maximum) propagation delay
  • 25-ns (maximum) part-to-part delay matching
  • 35-ns (maximum) pulse width distortion
  • 150-kV/μs (minimum) common-mode transient immunity (CMTI)
  • Isolation barrier life >50 Years
  • 13-V reverse polarity voltage handling capability on input stage supporting interlock
  • Stretched SO-6 package with >8.5-mm creepage and clearance
  • Operating junction temperature, TJ: –40°C to +150°C
  • Functional Safety-Capable
  • Safety-related certifications:
    • 8000-VPK reinforced isolation per DIN V VDE V0884-11: 2017-01 (In Progress)
    • 5.7-kVRMS isolation for 1 minute per UL 1577