Product details

Sample rate (max) (Msps) 1000 Resolution (Bits) 12 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 68.4 ENOB (Bits) 11.1 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1000 Resolution (Bits) 12 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 68.4 ENOB (Bits) 11.1 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 12-Bit Resolution, Dual-Channel, 1-GSPS ADC
  • Noise Floor: –157 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 67.8 dBFS
    • NSD: –155 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 65.6 dBFS
    • NSD: –152.6 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 10.0 Gbps
    • 4 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-Pin VQFNP (10 mm × 10 mm)
  • 12-Bit Resolution, Dual-Channel, 1-GSPS ADC
  • Noise Floor: –157 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 67.8 dBFS
    • NSD: –155 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and Interleaving Tones)
  • Spectral Performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 65.6 dBFS
    • NSD: –152.6 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (Except HD2, HD3, and Interleaving Tones)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Wideband DDC Block
  • JESD204B Interface with Subclass 1 Support:
    • 2 Lanes per ADC at 10.0 Gbps
    • 4 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-Pin VQFNP (10 mm × 10 mm)

The ADS54J20 is a low-power, wide-bandwidth, 12-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Optionally, each ADC channel can be connected to a wideband digital down-converter (DDC) block. The ADS54J20 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 12-bit data from each channel.

The ADS54J20 is a low-power, wide-bandwidth, 12-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Optionally, each ADC channel can be connected to a wideband digital down-converter (DDC) block. The ADS54J20 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 12-bit data from each channel.

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* Data sheet ADS54J20 Dual-Channel, 12-Bit, 1.0-GSPS, Analog-to-Digital Converter datasheet (Rev. B) PDF | HTML 20 Jan 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS54J20EVM — ADS54J20 Dual-Channel, 12-Bit, 1.0-GSPS Analog-to-Digital Converter Evaluation Module

The ADS54J20EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J20 and LMK04828 clock jitter cleaner. The ADS54J20 is a low power, 12-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. (...)
User guide: PDF
Not available on TI.com
Firmware

TI204C-IP Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

Supported products & hardware

Supported products & hardware

GUI for evaluation module (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

Supported products & hardware

Simulation model

ADS54J20/40/60 IBIS MODEL

SBAM205.ZIP (46 KB) - IBIS Model
Simulation model

ADS54J20/40/60 IBIS-AMI Model

SBAM325.ZIP (5519 KB) - IBIS-AMI Model
Calculation tool

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

Supported products & hardware

Supported products & hardware

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFNP (RMP) 72 Ultra Librarian

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