The ADS54J20 is a low-power, wide-bandwidth, 12-bit, 1.0-GSPS, dual-channel,
analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device
delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic
range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with
data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides
uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Optionally, each ADC channel can be connected to a wideband digital down-converter (DDC) block. The
ADS54J20 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range
with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system
integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to
derive the bit clock that is used to serialize the 12-bit data from each channel.
The ADS54J20 is a low-power, wide-bandwidth, 12-bit, 1.0-GSPS, dual-channel,
analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device
delivers a noise floor of –157 dBFS/Hz for applications aiming for highest dynamic
range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with
data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides
uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Optionally, each ADC channel can be connected to a wideband digital down-converter (DDC) block. The
ADS54J20 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range
with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system
integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to
derive the bit clock that is used to serialize the 12-bit data from each channel.