TI-JESD204-IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical constraints of the JESD204 protocol. The IP assists designers cut firmware development time and ease FPGA integration.

The JESD204 rapid design IP is provided royalty free for use with TI high-speed data converters. TI will assist the user in the configuration of the initial link, customized for use between the specific FPGA platform and TI data converter JMODE. TI will provide the IP via a secure download link after it is tested and ready for deployment.

The JESD204 rapid design IP supports the following FPGA families:

• Xilinx® Virtex™ UltraScale™ and UltraScale+™
• Xilinx Kintex™ UltraScale and UltraScale+
• Xilinx Zynq™ UltraScale+ and Zynq UltraScale+ (Auto)
• Xilinx Artix™ 7 and Artix 7 (Auto)
• Xilinx Virtex 7
• Xilinx Kintex 7 and Kintex 7 (Auto)
• Xilinx Zynq7000 and Zynq7000 (Auto)

Get Started

To get started with JESD204 rapid design IP:

• Step 1: Choose a TI high-speed data converter, the JESD204 mode and the FPGA for your system
• Step 2: Request JESD204 rapid design IP

• Compatible with JEDEC JESD204a/b/c protocols
• Supports subclass 1 deterministic latency and multidevice synchronization
• Supported lane rates
• Up to 16.375 Gbps in 8b/10b mode
• Up to 20 Gbps in 64b/66b mode
• Supports all protocol related error detection and reporting features
• Integrated transport layer converts lane data into samples (not supported for HD modes)
• Optimized logic and memory footprint in the FPGA, freeing up resources for application logic (and enabling smaller and lower-cost FPGAs where possible)
• Novel design features, including data export at clock rates that are asynchronous to the line rate