Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.25 Power consumption (typ) (mW) 3500 Architecture Pipeline SNR (dB) 68.3 ENOB (Bits) 11 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.25 Power consumption (typ) (mW) 3500 Architecture Pipeline SNR (dB) 68.3 ENOB (Bits) 11 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGC) 64 81 mm² 9 x 9
  • 4 Channel, 14-Bit 500 MSPS ADC
  • Analog input buffer with high impedance input
  • Flexible input clock buffer with divide by 1/2/4
  • 1.25 VPP Differential full-scale input
  • JESD204B Serial interface
    • Subclass 1 compliant up to 5 Gbps
    • 1 Lane Per ADC up to 250 Msps
    • 2 Lanes Per ADC up to 500 Msps
  • 64-Pin QFN Package (9 mm x 9 mm)
  • Key specifications:
    • Power dissipation: 875 mW/ch
    • Input bandwidth (3 dB): 900 MHz
    • Aperture jitter: 98 fs rms
    • Channel isolation: 85 dB
    • Performance at ƒin = 170 MHz at 1.25 VPP,
      1lane 2x Decimation –1 dBFS
      • SNR: 67.2 dBFS
      • SFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3
    • Performance at ƒin = 370 MHz at 1.25 VPP,
      2lane no Decimation –1 dBFS
      • SNR: 64.7 dBFS
      • SFDR: 75 dBc HD2,3; 83 dBFS non-HD2,3
  • 4 Channel, 14-Bit 500 MSPS ADC
  • Analog input buffer with high impedance input
  • Flexible input clock buffer with divide by 1/2/4
  • 1.25 VPP Differential full-scale input
  • JESD204B Serial interface
    • Subclass 1 compliant up to 5 Gbps
    • 1 Lane Per ADC up to 250 Msps
    • 2 Lanes Per ADC up to 500 Msps
  • 64-Pin QFN Package (9 mm x 9 mm)
  • Key specifications:
    • Power dissipation: 875 mW/ch
    • Input bandwidth (3 dB): 900 MHz
    • Aperture jitter: 98 fs rms
    • Channel isolation: 85 dB
    • Performance at ƒin = 170 MHz at 1.25 VPP,
      1lane 2x Decimation –1 dBFS
      • SNR: 67.2 dBFS
      • SFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3
    • Performance at ƒin = 370 MHz at 1.25 VPP,
      2lane no Decimation –1 dBFS
      • SNR: 64.7 dBFS
      • SFDR: 75 dBc HD2,3; 83 dBFS non-HD2,3

The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.

The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.

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* Data sheet ADS54J54 Quad Channel 14-Bit 500 MSPS ADC datasheet (Rev. A) PDF | HTML 01 Aug 2019
User guide Pipeline ADC Code Error Rate Analysis and Measurement 03 Nov 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS54J54EVM — ADS54J54 Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter Evaluation Module

The ADS54J54 EVM demonstrates the performance of a quad 500Msps 14 bit ADC with the JESD204B interface. It includes the ADS54J54 device and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for each channel of the ADC is by default (...)

User guide: PDF
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Firmware

TI204C-IP Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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GUI for evaluation module (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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GUI for evaluation module (EVM)

SLAC624 ADS54J54 EVM SPI GUI Installer v1.1

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Simulation model

ADS54J54 IBIS-AMI Model

SLAM308.ZIP (1371 KB) - IBIS-AMI Model
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Calculation tool

ANALOG-ENGINEER-CALC PC software analog engineer's calculator

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Supported products & hardware

Supported products & hardware

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGC) 64 Ultra Librarian

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