The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter datasheet (Rev. D) | PDF | HTML | 17 Apr 2019 |
| Application note | Implementing the External DC Offset Correction Block in the ADS54J60 (Rev. A) | PDF | HTML | 13 Jun 2023 | |
| User guide | HSDC Pro with Xilinx KCU105 | 01 Mar 2017 | ||
| Technical article | How to minimize filter loss when you drive an ADC | PDF | HTML | 20 Oct 2016 | |
| Analog Design Journal | JESD204B over optical fiber enables new architecture for phased-array radar | 26 Jan 2016 | ||
| Technical article | RF sampling: interleaving builds faster ADCs | PDF | HTML | 29 Oct 2015 | |
| Technical article | RF sampling: How over-sampling is cheating physics | PDF | HTML | 21 Aug 2015 |
For additional terms or required resources, click any title below to view the detail page where available.
The ADS54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60 and LMK04828 clock jitter cleaner. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. (...)
The TSW54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60, LMH3401, LMH6401 and LMK04828 devices. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)
The Abaco FMC120 provides four 16-bit analog-to-digital converters (ADCs) and four 16-bit digital-to-analog converters (DACs). The module highlights two products from Texas Instruments: the ADS54J60 two-channel, 16-bit, 1-GSPS ADC (two) and the DAC39J84 four-channel, 16-bit, 2.8-GSPS DAC (one) in a (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |
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Calculator installer
General calculator tool for analog design support.
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