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LMK00804B

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Low skew, 1-to-4 multiplexed differential/LVCMOS-to-LVCMOS/TTL fanout buffer

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Data sheet

LMK00804B

ACTIVE
Data sheet Order now

Product details

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  • Four LVCMOS/LVTTL Outputs with 7 Ω Output
    Impedance
    • Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz
    • Noise Floor: –166 dBc/Hz (typ) @ 125 MHz
    • Output Frequency: 350 MHz (max)
    • Output Skew: 35 ps (max)
    • Part-to-Part Skew: 700 ps (max)
  • Two Selectable Inputs
    • CLK, nCLK Pair Accepts LVPECL, LVDS,
      HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
    • LVCMOS_CLK Accepts LVCMOS/LVTTL
  • Synchronous Clock Enable
  • Core/Output Power Supplies:
    • 3.3 V/3.3 V
    • 3.3 V/2.5 V
    • 3.3 V/1.8 V
    • 3.3 V/1.5 V
  • Package: 16-Lead TSSOP
  • Industrial Temperature Range: –40ºC to +85ºC
  • Four LVCMOS/LVTTL Outputs with 7 Ω Output
    Impedance
    • Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz
    • Noise Floor: –166 dBc/Hz (typ) @ 125 MHz
    • Output Frequency: 350 MHz (max)
    • Output Skew: 35 ps (max)
    • Part-to-Part Skew: 700 ps (max)
  • Two Selectable Inputs
    • CLK, nCLK Pair Accepts LVPECL, LVDS,
      HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
    • LVCMOS_CLK Accepts LVCMOS/LVTTL
  • Synchronous Clock Enable
  • Core/Output Power Supplies:
    • 3.3 V/3.3 V
    • 3.3 V/2.5 V
    • 3.3 V/1.8 V
    • 3.3 V/1.5 V
  • Package: 16-Lead TSSOP
  • Industrial Temperature Range: –40ºC to +85ºC

The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.

See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts.

The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.

See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts.
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Technical documentation

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Type Title Date
* Data sheet LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer datasheet (Rev. A) PDF | HTML 07 Jul 2014
EVM User's guide LMK00804BEVM User’s Guide 27 Jun 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK00804B-Q1EVM — 4-output low-jitter differential/LVCMOS-to-LVCMOS fan-out buffer evaluation board

The LMK00804B-Q1 is a low skew, high performance clock fan-out buffer, which distributes up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels).  The clocks are derived from one of two selectable inputs, which can accept differential or single-ended input signals. The (...)
User guide: PDF
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Evaluation board

LMK00804BEVM — LMK00804BEVM 4-Output Low-Jitter Differential/LVCMOS-to-LVCMOS Fanout Buffer Evaluation Board

The LMK00804B is a low skew, high performance clock fanout buffer, which distributes up to four LVCMOS/LVTTL outputs (3.3V, 2.5V, 1.8V, or 1.5V levels).  The clocks are derived from one of two selectable inputs, which can accept differential or single-ended input signals. This evaluation (...)

User guide: PDF
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User guide: PDF | HTML
Simulation model

LMK00804B IBIS Model (Rev. A)

SNAM166A.ZIP (55 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Simulation tool

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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