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LMK5C33216A

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Three DPLL, three APLL, two-input and 16-output network synchronizer with JESD204B/C and BAW VCO

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Data sheet

LMK5C33216A

ACTIVE
Data sheet Order now

Product details

Function Clock network synchronizer Number of outputs 16 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 105 Number of input channels 2
Function Clock network synchronizer Number of outputs 16 Output type CML, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features JESD204B Output frequency (min) (MHz) 0.000000000001 Output frequency (max) (MHz) 3000 Input type HCSL, LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 105 Number of input channels 2
VQFN (RGC) 64 81 mm² 9 x 9
  • Ultra-low jitter BAW VCO based Wireless clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
    • Programmable DPLL loop bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • 16 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
    • Up to 20 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 14 differential outputs on OUT[15:0]_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • –40°C to 85°C operating temperature
  • Ultra-low jitter BAW VCO based Wireless clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
    • Programmable DPLL loop bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • 16 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
    • Up to 20 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 14 differential outputs on OUT[15:0]_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • –40°C to 85°C operating temperature

The LMK5C33216A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5C33216A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.
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Technical documentation

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* Data sheet LMK5C33216A 3-DPLL 3-APLL 2-IN 16-OUT Network Synchronizer With JED204B/JED204C and BAW VCO for Wireless Communications datasheet (Rev. A) PDF | HTML 05 Feb 2025
Application note Termination Guidelines for Differential and Single-Ended Signals PDF | HTML 10 Dec 2025
Application note The Debug Guide for Network Synchronizers (Digital and Analog Phase-Locked Loops) PDF | HTML 21 Nov 2025
User guide LMK5C33216A Programmer's Guide (Rev. A) PDF | HTML 17 Nov 2025
Application note Oscillator Power Considerations for PLL Devices PDF | HTML 30 Oct 2025
Certificate LMK5C33216AEVM EU Declaration of Conformity (DoC) 28 Sep 2023

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK5C33216AEVM — LMK5C33216A evaluation module

The LMK5C33216A evaluation module (EVM) is for the LMK5C33216A network clock generator and synchronizer. The EVM can be used for device evaluation, compliance testing and system prototyping. The LMK5C33216A integrates three Analog PLLs (APLL) and three Digital PLLs (DPLL) with programmable loop (...)

User guide: PDF | HTML
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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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Simulation model

LMK5B33216 Family IBIS model

SNAM295.ZIP (239 KB) - IBIS Model
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Design tool

CLOCK-PERFDATA-DESIGN — Clock performance data and register settings for clock generators, network synchronizers, jitter cleaners, and other clocking devices.

Configuration, raw phase noise data, noise plots, and register data for common use cases on clock generators, network synchronizers, jitter cleaners, and other clocking devices
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Design tool

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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Supported products & hardware
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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