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SN74CBTD3306

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5-V, 1:1 (SPST), 2-channel FET bus switch with level shifting

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SN74CBT3306C ACTIVE 5-V, 1:1 (SPST), 2-channel FET bus switch with –2-V undershoot protection (active low) Upgraded powered-off protection and undershoot protection support

SN74CBTD3306

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Product details

Protocols Analog Configuration 1:1 SPST Number of channels 2 Bandwidth (MHz) 20 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 4 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 50000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 2 Bandwidth (MHz) 20 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 4 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 50000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
TSSOP (PW) 8 19.2 mm² (3 mm × 6.4 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Designed to Be Used in Level-Shifting Applications
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Designed to Be Used in Level-Shifting Applications

The SN74CBTD3306 features two independent line switches. Each switch is disabled when the associated output-enable (OE\) input is high. A diode to VCC is integrated on the chip to allow for level shifting between 5-V inputs and 3.3-V outputs.

The SN74CBTD3306 features two independent line switches. Each switch is disabled when the associated output-enable (OE\) input is high. A diode to VCC is integrated on the chip to allow for level shifting between 5-V inputs and 3.3-V outputs.
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Technical documentation

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* Data sheet SN74CBTD3306 datasheet (Rev. L) Jan 15, 2004
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML Jun 2, 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML Dec 1, 2021

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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Simulation model

SN74CBTD3306 IBIS Model

SCDM001.ZIP (14 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
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