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SN74CBTLV3126

ACTIVE

3.3-V, 1:1 (SPST), 4-channel FET bus switch

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Data sheet

SN74CBTLV3126

ACTIVE
Data sheet Order now

Product details

Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 7 CON (typ) (pF) 2.5 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Supply voltage (max) (V) 3.6 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 7 CON (typ) (pF) 2.5 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
SOIC (D) 14 51.9 mm² 8.65 x 6 SSOP (DBQ) 16 29.4 mm² 4.9 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Standard 126-type pinout
  • 5Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • Standard 126-type pinout
  • 5Ω switch connection between two ports
  • Rail-to-rail switching on data I/O ports
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II

The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature verifies that damaging current does not backflow through the device when powered down. The SN74CBTLV3126 device has isolation during power off.

To verify the high-impedance state during power up or power down, tie OE to GND through a pull down resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature verifies that damaging current does not backflow through the device when powered down. The SN74CBTLV3126 device has isolation during power off.

To verify the high-impedance state during power up or power down, tie OE to GND through a pull down resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74CBTLV3126 Low-Voltage Quadruple FET Bus Switch datasheet (Rev. M) PDF | HTML 20 Jan 2026
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dec 2021
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 06 Jan 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 Nov 2004
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 01 Dec 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

User guide: PDF
Not available on TI.com
Simulation model

HSPICE Model for SN74CBTLV3126

SCDJ029.ZIP (96 KB) - HSpice Model
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Simulation model

SN74CBTLV3126 IBIS Model

SCDM079.ZIP (25 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SSOP (DBQ) 16 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
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