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SN74LV08A

ACTIVE

4-ch, 2-input 2-V to 5.5-V high-speed (7 ns) AND gate

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Data sheet

SN74LV08A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model

This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation. The SN74LV08A device performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.

This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation. The SN74LV08A device performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.
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Technical documentation

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* Data sheet SN74LV08A Quadruple 2-Input Positive-AND Gates datasheet (Rev. M) PDF | HTML 13 Oct 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LV08A Behavioral SPICE Model

SCLM190.ZIP (7 KB) - PSpice Model
Download
Simulation model

SN74LV08A IBIS Model

SCEM122.ZIP (16 KB) - IBIS Model
Download
Simulation model

SN74LV08A PSPICE MODEL

SCEM568.ZIP (1 KB) - PSpice Model
Download
Reference designs

TIDA-01365 — Bidirectional RS-485 Fan-Out Hub Reference Design

The Bidirectional RS-485 Fan-Out Hub Reference Design (TIDA-01365) documents and tests an RS-485 fan-out hub design where 1:N and N:1 RS-485 signals are aggregated in and out of any bus topology. This design also features automatic direction control, for reduced pin count on microcontrollers, and (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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