TMS320VC5401

Name: TMS320VC5401
Brand: TI
SKU: TMS320VC5401
Price: 3.493 USD

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Fixed-Point Digital Signal Processor

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Data sheet

document-pdfAcrobat TMS320VC5401 Fixed-Point Digital Signal Processor datasheet (Rev. D)

Errata

document-pdfAcrobat
TMS320VC5401 Silicon Errata

TMS320VC5401

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Data sheet

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Product details

DSP type

1 C54x

DSP (max) (MHz)

50

CPU

16-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

0 to 0

DSP type

1 C54x

DSP (max) (MHz)

50

CPU

16-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

0 to 0

LQFP (PGE)

144

484 mm² 22 x 22

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
4K x 16-Bit On-Chip ROM
8K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Efficient Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand Reads
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank Switching
- On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
- Two Multichannel Buffered Serial Ports (McBSPs)
- Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
- Two 16-Bit Timers
- Six-Channel Direct Memory Access (DMA) Controller
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
20-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS) for 3.3-V Power Supply (1.8-V Core)
144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
144-Ball MicroStar BGA™ (GGU Suffix)

IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
4K x 16-Bit On-Chip ROM
8K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Efficient Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand Reads
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank Switching
- On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
- Two Multichannel Buffered Serial Ports (McBSPs)
- Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
- Two 16-Bit Timers
- Six-Channel Direct Memory Access (DMA) Controller
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
20-ns Single-Cycle Fixed-Point Instruction Execution Time (50 MIPS) for 3.3-V Power Supply (1.8-V Core)
144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
144-Ball MicroStar BGA™ (GGU Suffix)

IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
TMS320C54x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners

The TMS320VC5401 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

The TMS320VC5401 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

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	Type	Title	Date
*	Data sheet	TMS320VC5401 Fixed-Point Digital Signal Processor datasheet (Rev. D)	17 Oct 2008
*	Errata	TMS320VC5401 Silicon Errata	31 Jul 2001
	User guide	TMS320C54x Chip Support Library API Reference Guide (Rev. D)	05 May 2003
	User guide	TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G)	31 Mar 2001
	User guide	TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C)	31 Jan 2001
	User guide	TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C)	31 Jan 2001
	User guide	TMS320C54x DSP Applications Guide Reference Set Volume 4	01 Oct 1996

Design & development

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Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com

Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)