(JTAG) Boundary Scan LogicIEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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TMS320C54x is a trademark of Texas Instruments.
This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404 (hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407 and 5404 are essentially the same device except for differences in their memory maps.
This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).
The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.
This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | TMS320VC5407/TMS320VC5404 Fixed-Point Digital Signal Processors datasheet (Rev. E) | 20 Oct 2008 | |
| User guide | TMS320C54x Chip Support Library API Reference Guide (Rev. D) | 05 May 2003 | ||
| User guide | TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) | 31 Mar 2001 | ||
| User guide | TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) | 31 Jan 2001 | ||
| User guide | TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) | 31 Jan 2001 | ||
| User guide | TMS320C54x DSP Applications Guide Reference Set Volume 4 | 01 Oct 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)
The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| LQFP (PGE) | 144 | Ultra Librarian |
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