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DRA75xP, DRA74xP, DRA77xP, DRA76xP SoC for Automotive Infotainment Silicon Revision 1.0 Texas Instruments Jacinto 6 Plus Infotainment Family of Products
- SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P

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DRA75xP, DRA74xP, DRA77xP, DRA76xP SoC for Automotive Infotainment Silicon Revision 1.0 Texas Instruments Jacinto 6 Plus Infotainment Family of Products

1
Read This First
1. Support Resources
2. About This Manual
3. Information About Cautions and Warnings
4. Register, Field, and Bit Calls
5. Coding Rules
6. Flow Chart Rules
7. Glossary
8. Export Control Notice
9. DRA75xP, DRA74xP, DRA77xP, DRA76xP MIPI® Disclaimer
10. Trademarks
1 Introduction
1. 1.1 DRA75xP, DRA74xP, DRA77xP, DRA76xP Overview
2. 1.2 DRA75xP, DRA74xP, DRA77xP, DRA76xP Environment
3. 1.3 DRA75xP, DRA74xP, DRA77xP, DRA76xP Description
4. 1.4 DRA75xP, DRA74xP, DRA77xP, DRA76xP Family
5. 1.5 DRA75xP, DRA74xP, DRA77xP, DRA76xP Device Identification
6. 1.6 DRA75xP, DRA74xP, DRA77xP, DRA76xP Package Characteristics Overview
2 Memory Mapping
1. 2.1 Introduction
2. 2.2 L3_MAIN Memory Map
  1. 2.2.1 L3_INSTR Memory Map
3. 2.3 L4 Memory Map
  1. 2.3.1 L4_CFG Memory Map
  2. 2.3.2 L4_WKUP Memory Map
4. 2.4 L4_PER Memory Map
5. 2.5 MPU Memory Map
6. 2.6 IPU Memory Map
7. 2.7 DSP Memory Map
8. 2.8 EVE Memory Map
9. 2.9 TILER View Memory Map
3 Power, Reset, and Clock Management
1. 3.1 Device Power Management Introduction
  1. 3.1.1 Device Power-Management Architecture Building Blocks
  2. 3.1.2 Power-Management Techniques
2. 3.2 PRCM Subsystem Overview
  1. 3.2.1 Introduction
  2. 3.2.2 Power-Management Framework Features
3. 3.3 PRCM Subsystem Environment
4. 3.4 PRCM Subsystem Integration
  1. 3.4.1 Device Power-Management Layout
  2. 3.4.2 Power-Management Scheme, Reset, and Interrupt Requests
5. 3.5 Reset Management Functional Description
6. 3.6 Clock Management Functional Description
7. 3.7 Power Management Functional Description
8. 3.8 Voltage-Management Functional Description
9. 3.9 Device Low-Power States
10. 3.10 PRCM Module Programming Guide
11. 3.11 560
12. 3.12 PRCM Software Configuration for OPP_PLUS
13. 3.13 PRCM Register Manual
4 Dual Cortex-A15 MPU Subsystem
1. 4.1 Dual Cortex-A15 MPU Subsystem Overview
  1. 4.1.1 Introduction
  2. 4.1.2 Features
2. 4.2 Dual Cortex-A15 MPU Subsystem Integration
  1. 4.2.1 Clock Distribution
  2. 4.2.2 Reset Distribution
3. 4.3 Dual Cortex-A15 MPU Subsystem Functional Description
4. 4.4 Dual Cortex-A15 MPU Subsystem Register Manual
5 DSP Subsystems
1. 5.1 DSP Subsystems Overview
  1. 5.1.1 DSP Subsystems Key Features
2. 5.2 DSP Subsystem Integration
3. 5.3 DSP Subsystems Functional Description
4. 5.4 DSP Subsystem Register Manual
6 IVA Subsystem
7 Dual Cortex-M4 IPU Subsystem
1. 7.1 Dual Cortex-M4 IPU Subsystem Overview
  1. 7.1.1 Introduction
  2. 7.1.2 Features
2. 7.2 Dual Cortex-M4 IPU Subsystem Integration
  1. 7.2.1 Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution
    1. 7.2.1.1 Clock Distribution
    2. 7.2.1.2 Reset Distribution
3. 7.3 Dual Cortex-M4 IPU Subsystem Functional Description
4. 7.4 Dual Cortex-M4 IPU Subsystem Register Manual
8 Embedded Vision Engine
1. 8.1 Embedded Vision Engine (EVE) Subsystem
2. 8.2 ARP32 CPU and Instruction Set
  1. 8.2.1 Overview
  2. 8.2.2 Features
  3. 8.2.3 Block Diagram
  4. 8.2.4 Architecture
  5. 8.2.A Instruction Set
    1. 8.2.A.1 Instruction Operation and Execution Notations
    2. 8.2.A.2 Instruction Syntax and Opcode Notations
    3. 8.2.A.3 Instruction Scheduling Restrictions
    4. 8.2.A.4 Instruction Set Encoding
    5. 8.2.A.5 Instruction Descriptions
      1. ABS
      2. ADD
      3. ADD
      4. ADD
      5. ADD
      6. ADD
      7. AND
      8. AND
      9. B(cc)
      10. B(cc)
      11. B(cc)
      12. BIRP
      13. BKPT
      14. BNRP
      15. CALL
      16. CALL
      17. CLR
      18. CLR
      19. CMP
      20. CMP
      21. CMP
      22. CMPU
      23. CMPU
      24. CMPU
      25. DIV
      26. DIVU
      27. EXT
      28. EXT
      29. EXTU
      30. EXTU
      31. IDLE
      32. LDB(U)
      33. LDB(U)
      34. LDB(U)
      35. LDB(U)
      36. LDB(U)
      37. LDB(U)
      38. LDB(U)
      39. LDB(U)
      40. LDH(U)
      41. LDH(U)
      42. LDH(U)
      43. LDH(U)
      44. LDH(U)
      45. LDH(U)
      46. LDH(U)
      47. LDH(U)
      48. LDW
      49. LDW
      50. LDW
      51. LDW
      52. LDW
      53. LDW
      54. LDW
      55. LDW
      56. LDRF
      57. LMBD
      58. MAX
      59. MAXU
      60. MIN
      61. MINU
      62. MOD
      63. MODU
      64. MPY
      65. MPYU
      66. MV
      67. MVC
      68. MVC
      69. MVC
      70. MVCH
      71. MVK
      72. MVKH
      73. MVKLS
      74. MVKS
      75. MVS
      76. MVS
      77. NEG
      78. NOP
      79. NOT
      80. OR
      81. OR
      82. RET
      83. REV
      84. ROT
      85. ROTC
      86. SADD
      87. SATN
      88. SET
      89. SET
      90. SHL
      91. SHL
      92. SHRA
      93. SHRA
      94. SHRU
      95. SHRU
      96. SLA
      97. SSUB
      98. STB
      99. STB
      100. STB
      101. STB
      102. STB
      103. STB
      104. STB
      105. STB
      106. STH
      107. STH
      108. STH
      109. STH
      110. STH
      111. STH
      112. STH
      113. STH
      114. STW
      115. STW
      116. STW
      117. STW
      118. STW
      119. STW
      120. STW
      121. STW
      122. STHI
      123. STRF
      124. SUB
      125. SUB
      126. SUB
      127. SUB
      128. SUB
      129. SWI
      130. XOR
      131. XOR
  6. 8.2.B Clock, Reset, and Dynamic Power Management
    1. 8.2.B.1 Introduction
    2. 8.2.B.2 CPU Reset Modes
    3. 8.2.B.3 Dynamic Power Management
  7. 8.2.C Notes on Programming Model
    1. 8.2.C.1 Booting
    2. 8.2.C.2 Enabling and Disabling Interrupts
      1. 8.2.C.2.1 Globally Enabling or Disabling Maskable Interrupts
      2. 8.2.C.2.2 Enabling or Disabling Individual Interrupts
    3. 8.2.C.3 Stack Usage in Interrupt Service Routine
    4. 8.2.C.4 General Restrictions
3. 8.3 VCOP CPU and Instruction Set
9 Imaging Subsystem
1. 9.1 ISS Overview
2. 9.2 ISS Camera Adapter Layer (CAL)
3. 9.3 ISS Image Signal Processor (ISP)
4. 9.4 ISS Still Image Coprocessor (SIMCOP)
10Camera Interface Subsystem
1. 10.1 CAMSS Overview
2. 10.2 CAMSS Environment
  1. 10.2.1 CAMSS Interfaces Signal Descriptions
3. 10.3 CAMSS Integration
4. 10.4 CAMSS Functional Description
5. 10.5 CAMSS Register Manual
11Video Input Port
1. 11.1 VIP Overview
2. 11.2 VIP Environment
3. 11.3 VIP Integration
4. 11.4 VIP Functional Description
5. 11.5 VIP Register Manual
12Video Processing Engine
1. 12.1 VPE Overview
2. 12.2 VPE Integration
3. 12.3 VPE Functional Description
4. 12.4 VPE Register Manual
13Display Subsystem
1. 13.1 Display Subsystem Overview
2. 13.2 Display Controller
3. 13.3 High-Definition Multimedia Interface
  1. 13.3.1 HDMI Overview
    1. 13.3.1.1 HDMI Main Features
    2. 13.3.1.2 HDMI Video Formats and Timings
      1. 13.3.1.2.1 HDMI CEA-861-D Video Formats and Timings
      2. 13.3.1.2.2 VESA DMT Video Formats and Timings
143D Graphics Accelerator
1. 14.1 GPU Overview
  1. 14.1.1 GPU Features Overview
  2. 14.1.2 Graphics Feature Overview
2. 14.2 GPU Integration
3. 14.3 GPU Functional Description
4. 14.4 GPU Register Manual
  1. 14.4.1 GPU Instance Summary
  2. 14.4.2 GPU Registers
    1. 14.4.2.1 GPU_WRAPPER Register Summary
    2. 14.4.2.2 GPU_WRAPPER Register Description
152D Graphics Accelerator
1. 15.1 BB2D Overview
  1. 15.1.1 BB2D Key Features Overview
2. 15.2 BB2D Integration
3. 15.3 BB2D Functional Description
4. 15.4 BB2D Register Manual
  1. 15.4.1 BB2D Instance Summary
  2. 15.4.2 BB2D Registers
    1. 15.4.2.1 BB2D Register Summary
    2. 15.4.2.2 BB2D Register Description
16Interconnect
1. 16.1 Interconnect Overview
  1. 16.1.1 Terminology
  2. 16.1.2 Architecture Overview
2. 16.2 L3_MAIN Interconnect
3. 16.3 L4 Interconnects
17Memory Subsystem
1. 17.1 Memory Subsystem Overview
2. 17.2 Dynamic Memory Manager
3. 17.3 EMIF Controller
4. 17.4 General-Purpose Memory Controller
5. 17.5 Error Location Module
6. 17.6 On-Chip Memory (OCM) Subsystem
18DMA Controllers
1. 18.1 System DMA
2. 18.2 Enhanced DMA
19Interrupt Controllers
1. 19.1 Interrupt Controllers Overview
2. 19.2 Interrupt Controllers Environment
3. 19.3 Interrupt Controllers Integration
4. 19.4 Interrupt Controllers Functional Description
20Control Module
1. 20.1 Control Module Overview
2. 20.2 Control Module Environment
3. 20.3 Control Module Integration
4. 20.4 Control Module Functional Description
5. 20.5 Control Module Register Manual
6. 20.6 IODELAYCONFIG Module Integration
7. 20.7 IODELAYCONFIG Module Register Manual
21Mailbox
1. 21.1 Mailbox Overview
2. 21.2 Mailbox Integration
3. 21.3 Mailbox Functional Description
4. 21.4 Mailbox Programming Guide
  1. 21.4.1 Mailbox Low-level Programming Models
5. 21.5 Mailbox Register Manual
  1. 21.5.1 Mailbox Instance Summary
  2. 21.5.2 Mailbox Registers
    1. 21.5.2.1 Mailbox Register Summary
    2. 21.5.2.2 Mailbox Register Description
22Memory Management Units
1. 22.1 MMU Overview
2. 22.2 MMU Integration
3. 22.3 MMU Functional Description
4. 22.4 MMU Low-level Programming Models
  1. 22.4.1 Global Initialization
5. 22.5 MMU Register Manual
  1. 22.5.1 MMU Instance Summary
  2. 22.5.2 MMU Registers
    1. 22.5.2.1 MMU Register Summary
    2. 22.5.2.2 MMU Register Description
23Spinlock
1. 23.1 Spinlock Overview
2. 23.2 Spinlock Integration
3. 23.3 Spinlock Functional Description
4. 23.4 Spinlock Programming Guide
  1. 23.4.1 Spinlock Low-level Programming Models
    1. 23.4.1.1 Surrounding Modules Global Initialization
    2. 23.4.1.2 Basic Spinlock Operations
      1. 23.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
      2. 23.4.1.2.2 Take and Release Spinlock
5. 23.5 Spinlock Register Manual
  1. 23.5.1 Spinlock Instance Summary
  2. 23.5.2 Spinlock Registers
    1. 23.5.2.1 Spinlock Register Summary
    2. 23.5.2.2 Spinlock Register Description
24Timers
1. 24.1 Timers Overview
2. 24.2 General-Purpose Timers
3. 24.3 32-kHz Synchronized Timer (COUNTER_32K)
4. 24.4 Watchdog Timer
25Real-Time Clock (RTC)
1. 25.1 RTC Overview
  1. 25.1.1 RTC Features
2. 25.2 RTC Environment
  1. 25.2.1 RTC External Interface
3. 25.3 RTC Integration
4. 25.4 RTC Functional Description
5. 25.5 RTC Low-Level Programming Guide
  1. 25.5.1 Global Initialization
    1. 25.5.1.1 Surrounding Modules Global Initialization
    2. 25.5.1.2 RTC Module Global Initialization
      1. 25.5.1.2.1 Main Sequence – RTC Module Global Initialization
6. 25.6 RTC Register Manual
  1. 25.6.1 RTC Instance Summary
  2. 25.6.2 RTC_SS Registers
    1. 25.6.2.1 RTC_SS Register Summary
    2. 25.6.2.2 RTC_SS Register Description
26Serial Communication Interfaces
1. 26.1 Multimaster High-Speed I2C Controller
2. 26.2 HDQ/1-Wire
3. 26.3 UART/IrDA/CIR
4. 26.4 Multichannel Serial Peripheral Interface
5. 26.5 Quad Serial Peripheral Interface
6. 26.6 Multichannel Audio Serial Port
7. 26.7 SuperSpeed USB DRD
8. 26.8 SATA Controller
9. 26.9 PCIe Controller
10. 26.10 DCAN
11. 26.11 MCAN
12. 26.12 Gigabit Ethernet Switch (GMAC_SW)
13. 26.13 Media Local Bus (MLB)
27eMMC/SD/SDIO
1. 27.1 eMMC/SD/SDIO Overview
  1. 27.1.1 eMMC/SD/SDIO Features
2. 27.2 eMMC/SD/SDIO Environment
  1. 27.2.1 eMMC/SD/SDIO Functional Modes
    1. 27.2.1.1 eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card
  2. 27.2.2 Protocol and Data Format
    1. 27.2.2.1 Protocol
    2. 27.2.2.2 Data Format
3. 27.3 eMMC/SD/SDIO Integration
4. 27.4 eMMC/SD/SDIO Functional Description
5. 27.5 eMMC/SD/SDIO Programming Guide
  1. 27.5.1 Low-Level Programming Models
    1. 27.5.1.1 Global Initialization
      1. 27.5.1.1.1 Surrounding Modules Global Initialization
      2. 27.5.1.1.2 eMMC/SD/SDIO Host Controller Initialization Flow
        
        27.5.1.1.2.1 Enable Interface and Functional Clock for MMC Controller
        
        27.5.1.1.2.2 MMCHS Soft Reset Flow
        
        27.5.1.1.2.3 Set MMCHS Default Capabilities
        
        27.5.1.1.2.4 Wake-Up Configuration
        
        27.5.1.1.2.5 MMC Host and Bus Configuration
    2. 27.5.1.2 Operational Modes Configuration
6. 27.6 eMMC/SD/SDIO Register Manual
  1. 27.6.1 eMMC/SD/SDIO Instance Summary
  2. 27.6.2 eMMC/SD/SDIO Registers
    1. 27.6.2.1 eMMC/SD/SDIO Register Summary
    2. 27.6.2.2 eMMC/SD/SDIO Register Description
28Shared PHY Component Subsystem
1. 28.1 SATA PHY Subsystem
2. 28.2 USB3_PHY Subsystem
3. 28.3 USB3 PHY and SATA PHY Register Manual
4. 28.4 PCIe PHY Subsystem
29General-Purpose Interface
1. 29.1 General-Purpose Interface Overview
2. 29.2 General-Purpose Interface Environment
  1. 29.2.1 General-Purpose Interface as a Keyboard Interface
  2. 29.2.2 General-Purpose Interface Signals
3. 29.3 General-Purpose Interface Integration
4. 29.4 General-Purpose Interface Functional Description
5. 29.5 General-Purpose Interface Programming Guide
  1. 29.5.1 General-Purpose Interface Low-Level Programming Models
    1. 29.5.1.1 Global Initialization
      1. 29.5.1.1.1 Surrounding Modules Global Initialization
      2. 29.5.1.1.2 General-Purpose Interface Module Global Initialization
    2. 29.5.1.2 General-Purpose Interface Operational Modes Configuration
6. 29.6 General-Purpose Interface Register Manual
  1. 29.6.1 General-Purpose Interface Instance Summary
  2. 29.6.2 General-Purpose Interface Registers
    1. 29.6.2.1 General-Purpose Interface Register Summary
    2. 29.6.2.2 General-Purpose Interface Register Description
30Keyboard Controller
1. 30.1 Keyboard Controller Overview
2. 30.2 Keyboard Controller Environment
3. 30.3 Keyboard Controller Integration
4. 30.4 Keyboard Controller Functional Description
5. 30.5 Keyboard Controller Programming Guide
  1. 30.5.1 Keyboard Controller Low-Level Programming Models
6. 30.6 Keyboard Controller Register Manual
  1. 30.6.1 Keyboard Controller Instance Summary
  2. 30.6.2 Keyboard Controller Registers
    1. 30.6.2.1 Keyboard Controller Register Summary
    2. 30.6.2.2 Keyboard Controller Register Description
31Pulse-Width Modulation Subsystem
1. 31.1 PWM Subsystem Resources
2. 31.2 Enhanced PWM (ePWM) Module
3. 31.3 Enhanced Capture (eCAP) Module
4. 31.4 Enhanced Quadrature Encoder Pulse (eQEP) Module
32Viterbi-Decoder Coprocessor
1. 32.1 VCP Overview
  1. 32.1.1 VCP Features
2. 32.2 VCP Integration
3. 32.3 VCP Functional Description
4. 32.4 VCP Modules Programming Guide
  1. 32.4.1 EDMA Resources
    1. 32.4.1.1 VCP1 and VCP2 Dedicated EDMA Resources
    2. 32.4.1.2 Special VCP EDMA Programming Considerations
  2. 32.4.2 Input Configuration Words
5. 32.5 VCP Register Manual
  1. 32.5.1 VCP1 and VCP2 Instance Summary
  2. 32.5.2 VCP Registers
33Audio Tracking Logic
1. 33.1 ATL Overview
2. 33.2 ATL Environment
  1. 33.2.1 ATL Functions
  2. 33.2.2 ATL Signals Descriptions
3. 33.3 ATL Integration
  1. 33.3.1 ATL Distribution on Interconnects
  2. 33.3.2 ATL Regions Allocations
4. 33.4 ATL Functional Description
5. 33.5 ATL Register Manual
34Initialization
1. 34.1 Initialization Overview
  1. 34.1.1 Terminology
  2. 34.1.2 Initialization Process
2. 34.2 Preinitialization
3. 34.3 Device Initialization by ROM Code
4. 34.4 Services for HLOS Support
35On-Chip Debug Support
1. 35.1 Introduction
  1. 35.1.1 Key Features
2. 35.2 Debug Interfaces
3. 35.3 Debugger Connection
4. 35.4 Primary Debug Support
5. 35.5 Real-Time Debug
  1. 35.5.1 Real-Time Debug Events
    1. 35.5.1.1 Emulation Interrupts
6. 35.6 Power, Reset, and Clock Management Debug Support
  1. 35.6.1 Power and Clock Management
    1. 35.6.1.1 Power and Clock Control Override From Debugger
      1. 35.6.1.1.1 Debugger Directives
        
        35.6.1.1.1.1 FORCEACTIVE Debugger Directive
        
        35.6.1.1.1.2 INHIBITSLEEP Debugger Directive
      2. 35.6.1.1.2 Intrusive Debug Model
    2. 35.6.1.2 Debug Across Power Transition
      1. 35.6.1.2.1 Nonintrusive Debug Model
      2. 35.6.1.2.2 Debug Context Save and Restore
        
        35.6.1.2.2.1 Debug Context Save
        
        35.6.1.2.2.2 Debug Context Restore
  2. 35.6.2 Reset Management
    1. 35.6.2.1 Debugger Directives
7. 35.7 Performance Monitoring
8. 35.8 MPU Memory Adaptor (MPU_MA) Watchpoint
9. 35.9 Processor Trace
10. 35.10 System Instrumentation
11. 35.11 Concurrent Debug Modes
12. 35.12 DRM Register Manual
  1. 35.12.1 DRM Instance Summary
  2. 35.12.2 DRM Registers
    1. 35.12.2.1 DRM Register Summary
    2. 35.12.2.2 DRM Register Description
36Revision History
IMPORTANT NOTICE

Full reading width