SDAA100 April   2026 ADC12DJ5200RF , ADC32RF54 , ADC32RF55 , LMX2572 , LMX2594 , LMX2820

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Effects of a Phase Noise Curve of a Clock on the Performance of the Converter
  6. 3 Determine Clock Performance Target Values for a Selected Data Converter
  7. 4 Narrow Down Which TI Clock to Select Based on the Specified Requirements Determined
  8. 5 Analyze the Proposed Clock's Jitter on a Converter's Performance
  9. 6 Understanding Clocking Performance Effects on the SNR of the Converter
    1. 6.1 Limitations from TI Clocking Parts When Paired with TI High-Speed Converters
  10. 7 Summary
  11. 8 References
  12. 9 Appendix A: Clock Tree Architect (CTA) Detailed Step-By-Step Guide
  13. 10Appendix B: Using PLLatinum Sim to Represent Clock Jitter for an Application's Integrated Bandwidth
  14. 11Appendix C: PLLatinum Sim Phase Noise Curves Comparison Step-by-Step Guide
  15. 12Appendix D: Comparing Phase Noise Curve Simulations of PLLatinum Sim with Measured Data
Application Note

Leveraging TI Clock Tools For Data Converter Designs