GUI for evaluation module (EVM)
ADC32RF55EVM-GUI — ADC3xRF5xEVM GUI installer/configuration generator
ADC3xRF5xEVM GUI installer/configuration generator
ADC32RF54
Dual-channel 14-bit 2.6-GSPS RF-sampling ADC with low noise spectral density (NSD)
Data sheet
ADC32RF54
- 14-Bit, dual channel 2.6 to 3-GSPS ADC
- Noise spectral density:
- NSD = -155.6 dBFS/Hz (no AVG)
- NSD = -158.1 dBFS/Hz (2x AVG)
- NSD = -160.4 dBFS/Hz (4x AVG)
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 50 fs
- Low close-in residual phase noise:
- -127 dBc/Hz at 10 kHz offset
- Spectral performance (f IN = 1 GHz, -4 dBFS):
- 2x internal averaging
- SNR: 62.3 dBFS
- SFDR HD2,3: 63 dBc
- SFDR worst spur: 85 dBFS
- Spectral performance (f IN = 1.8 GHz, -4 dBFS):
- 2x internal averaging
- SNR: 63 dBFS
- SFDR HD2,3: 68 dBc
- SFDR worst spur: 86 dBFS
- Input fullscale: 1.1 to 1.35 Vpp (2 to 3.5 dBm)
- Code error rate (CER): 10 -15
- Full power input bandwidth (-3 dB): 2.75 GHz
- JESD204B serial data interface
- Maximum lane rate: 13 Gbps
- Supports subclass 1 deterministic latency
- Digital down-converters
- Up to four DDC per ADC channel
- Complex output: 4x to 128x decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1 us
- Power consumption: 2.6 W/channel (2x AVG)
- Power supplies: 1.8 V, 1.2 V
The ADC32RF5x is a single core 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converters (ADC) that supports RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -161 dBFS/Hz.
Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs.
The ADC32RF54 and ADC32RF55 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps.
The power efficient ADC architecture consumes 2.1 W/ch at 3 Gsps and provides power scaling with lower sampling rates.
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Technical documentation
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View all 7 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC32RF5x Dual Channel 14-bit 2.6 to 3-GSPS RF Sampling Data Converter datasheet (Rev. B) | PDF | HTML | 21 Aug 2023 |
| Application brief | Noise Spectral Density: A Better Way (Rev. A) | PDF | HTML | 18 May 2024 | |
| Analog Design Journal | ADC 雜訊指數如何影響 RF 接收器設計 | PDF | HTML | 01 Dec 2023 | |
| Analog Design Journal | ADC 잡음 수치가 RF 수신기 설계에 미치는 영향 | PDF | HTML | 01 Dec 2023 | |
| Analog Design Journal | How the ADC noise figure impacts RF receiver designs | PDF | HTML | 20 Jul 2023 | |
| Application note | Improve SFDR Using Calibration in High-Speed ADCs | PDF | HTML | 19 Jun 2023 | |
| Application note | Getting the Most of Your Data Converter Clocking System Using LMX1204 | PDF | HTML | 23 Jun 2022 |
Design & development
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Evaluation board
ADC32RF54EVM — ADC32RF55 evaluation module for dual-channel 14-bit 2.6-GSPS RF-sampling ADC with low NSD
The ADC32RF54 evaluation module (EVM) is a platform for demonstrating the performance of the ADC32RF54 high-speed, JESD204B interface analog-to-digital converter (ADC). Onboard voltage regulation, clocking solution (LMK04832), transformer-coupled analog inputs, and USB interface allow for easy (...)
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFNP (RTD) | 64 | Ultra Librarian |
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