The DP83TG721-Q1 is an IEEE 802.3bp and Open Alliance compliant automotive 1000Base-T1 Ethernet physical layer transceiver. The DP83TG721-Q1 provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables. The device provides xMII flexibility with support for RGMII and SGMII MAC interfaces.
DP83TG721-Q1 supports OA TC10 low power sleep feature (with wake forwarding) to reduce system power consumption when communication is not required. This device offers the Diagnostic Tool Kit, with an extensive list of real-time monitoring tools, debug tools and test modes.
DP83TG721-Q1 integrates IEEE 1588v2/802.1AS hardware time stamping & fractional PLL enabling highly accurate time synchronization. The fractional PLL enables frequency/phase synchronization of the Wall Clock eliminating need for external VCXO and generating wide range of time synchronized frequencies needed for Audio, Video and other ADAS applications.
DP83TG721-Q1 also integrates IEEE 1722 CRF decode to generate Media Clock (wall clock synchronized) for AVB & other Audio standards. The DP83TG721-Q1 is also capable of generating FSYNC/SCLK (wall clock synchronized) for I2S/TDM8 interface needed for audio applications.
The DP83TG721-Q1 is compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with single board for both speeds.
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | DP83TG721x-Q1 1000BASE-T1 Automotive Ethernet PHY with Advanced TSN and AVB datasheet (Rev. A) | PDF | HTML | 10 Jun 2024 |
| Application note | How to Integrate Linux Driver Into Your System | PDF | HTML | 12 Jul 2024 | |
| Certificate | DP83TG721EVM-MC EU RoHS Declaration of Conformity (DoC) | 04 Nov 2022 |
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RHA) | 36 | Ultra Librarian |
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