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Noninverting buffers & drivers

SN74AUP1G07

ACTIVE

Single 0.8-V to 3.6-V low power buffer with open-drain outputs

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Data sheet

SN74AUP1G07

ACTIVE
Data sheet Order now

Product details

Technology family AUP Number of channels 1 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Number of channels 1 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) 0 Input type Standard CMOS Output type Open-drain Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm) SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm) DSBGA (YZP) 5 2.1875 mm² (— mm × — mm) DSBGA (YFP) 4 1 mm² (— mm × — mm) SOT-5X3 (DRL) 5 2.56 mm² (1.6 mm × 1.6 mm)
  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 1 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 3.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 1 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 3.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

The SN74AUP1G07 device is a single buffer gate with open drain output that operates from 0.8 V to 3.6 V.

The SN74AUP1G07 device is a single buffer gate with open drain output that operates from 0.8 V to 3.6 V.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74AUP1G07 Low-Power Single Buffer/Driver With Open-Drain Outputs datasheet (Rev. J) PDF | HTML Dec 13, 2013
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML Apr 17, 2025
Application note Designing and Manufacturing with TI's X2SON Packages Aug 23, 2017

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SCEM691.ZIP (7 KB) - PSpice model
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X2SON (DPW) 5 Ultra Librarian
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