主页 逻辑和电压转换 触发器、锁存器和寄存器 JK 触发器
主页
逻辑和电压转换
触发器、锁存器和寄存器
JK 触发器

CD74AC109

正在供货

具有设置和复位端的双通道上升沿触发式 J-K 触发器

立即订购
数据表

CD74AC109

正在供货
数据表 立即订购

产品详情

Number of channels 2 Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 80 IOL (max) (mA) 24 IOH (max) (mA) -24 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 2 Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Input type LVTTL/CMOS Output type Push-Pull Clock frequency (MHz) 100 Supply current (max) (µA) 80 IOL (max) (mA) 24 IOH (max) (mA) -24 Features Balanced outputs, Clear, High speed (tpd 10-50ns), Positive edge triggered, Positive input clamp diode, Preset Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6
  • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
  • AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
  • Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • ±24-mA Output Drive Current
    • Fanout to 15 F Devices
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

The ’AC109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The ’AC109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
filter 查找其他 JK 触发器
下载

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相同，且具有相同引脚
SN74LVC112A 正在供货 具有清零和预设功能的双路下降沿 J-K 触发器 Smaller voltage range (1.65V to 3.6V), shorter propagation delay (5.5ns)

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 1
类型 标题 下载最新的英语版本 日期
* 数据表 CD54AC109, CD74AC109 数据表 2003年 1月 24日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训