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SN74S112A

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具有清零和预设功能的双通道 J-K 下降沿触发器

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数据表

SN74S112A

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数据表 立即订购

产品详情

Number of channels 2 Technology family S Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL Output type Push-Pull Clock frequency (MHz) 125 Supply current (max) (µA) 25000 IOL (max) (mA) 20 IOH (max) (mA) -1 Features Clear, High speed (tpd 10-50ns), Negative edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 2 Technology family S Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL Output type Push-Pull Clock frequency (MHz) 125 Supply current (max) (µA) 25000 IOL (max) (mA) 20 IOH (max) (mA) -1 Features Clear, High speed (tpd 10-50ns), Negative edge triggered, Preset Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 16 181.42 mm² 19.3 x 9.4
  • Fully Buffered to Offer Maximum Isolation from External Disturbance
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 
  • Fully Buffered to Offer Maximum Isolation from External Disturbance
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

 

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS112A and SN74S112A are characterized for operation from 0°C to 70°C.

 
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SN74LVC112A 正在供货 具有清零和预设功能的双路下降沿 J-K 触发器 Voltage range (1.65V to 3.6V), average drive strength (24mA), average propagation delay (5.5ns)

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类型 标题 下载最新的英语版本 日期
* 数据表 Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 数据表 1988年 3月 1日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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