This reference design demonstrates how to achieve multiple ADC interleaving with high sampling rates and good resolution at low BOM-cost. The reference design was built with electronic imaging systems in mind. High definition imaging and other high speed signal processing applications require ADCs that can achieve high resolution, high SNR, high speed and low power consumption. These requirements cannot always be met with a single chip. By interleaving multiple SAR ADCs, the design optimizes trade-offs between different ADCs in order to meet all of the system requirements.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | AFE Ref Design for Imaging Using Time-Interleaved SAR ADCs w/ 73dB SNR, 7.5 MSPS | Aug. 07, 2017 | |
| Application note | Low-Cost, Low-Power, Small 14-bit AFE: Interleaved ADCs Scalable up to 7.5 MSPS | May 26, 2017 |
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.