This design guide proposes power tree concept reference designs surrounding an Advanced Micro Devices® (AMD) Ultrascale+™ Multi-Processor System-on-Chip (MPSoC) Field-Programmable Gate Array (FPGA). The power trees leverage newer TI modules and MagPack™ technology to minimize size on constrained boards while maintaining competitive efficiency, performance, and cost.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Includes TI products in the design and potential alternatives.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Design guide | Power Delivery Architecture for AMD® Ultrascale+™ MPSoC | PDF | HTML | Apr 7, 2026 |
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