Isolated Delta-Sigma modulators offer interface options for both an externally and internally generated clock signal with either a CMOS interface or a LVDS interface. For devices with externally-provided clock source, for example AMC1306M25 with CMOS interface or AMC1305L25 with LVDS interface the clock signal is routed from the MCU to the Delta-Sigma modulator’s clock input, whereas for devices with an internally-provided clock source, the output bit-stream is synchronized to the internally generated clock, for exampleAMC1303M2520. There are also isolated Delta-Sigma modulator devices with Manchester coded output bit stream that support single-wire data and clock transfer, for example AMC1306E25. For all isolated Delta-Sigma modulators, the data output of the modulator provides a bit stream of digital ones and zeros that is shifted out synchronous to the clock edge.

Figure 2-1 shows a simplified example of CMOS interface with 3.3V I/O between the isolated Delta-Sigma modulator AMC1306M25 and a C2000 MCU TMS320F28379D. As the AMC1306M25 requires an externally-provided clock source, the clock signal is generated by the MCU TMS320F28379D and is provided to the Delta-Sigma modulators clock input, CLKIN. In parallel, the generated clock signal is also routed to the clock input to the MCUs Sigma-Delta Filter Module (SDFM) SD1_C1 (GPIO123). Depending on the system design there can be a clock buffer included in the clock interface between the MCU and the isolated Delta-Sigma modulator. The isolated data output DOUT of the Delta-Sigma modulator is directly connected to the MCUs Sigma-Delta Filter Module (SDFM) data input SD1_D1 (GPIO122).

Figure 2-1 Simplified AMC1306M25 Digital Interface to TMS320F28379D

Valid communication between the isolated Delta-Sigma modulator and the MCU is described in the respective device data sheets by the setup and hold timing requirements. The setup time is the amount of time that the data signal must be valid and stable prior to a clock signal transition to capture the data signal in the MCU. Hold time is the amount of time that a signal must be held valid and stable after a clock signal transition occurs. Meeting the MCUs setup and hold time requirements is crucial as any violation can cause incorrect data to be captured. Incompatibility between the digital interface setup and hold timing requirements of the isolated Delta-Sigma modulator and the MCU can present a design challenge.

Figure 2-2 outlines the digital interface timing for setup and hold time of the AMC1306x which supports a recommended clock frequency (CLKIN) from 5 MHz to 21 MHz with a data hold time t_h(MIN) = 3.5 ns and a data delay time t_d (MAX) = 15 ns.

Figure 2-2 AMC1306x Digital Interface Timing

Figure 2-3 outlines the timing diagram, of the TMS320F28379D Sigma-Delta Filter Module (SDFM) for Mode 0. The data input at SDx_Dy needs to meet the minimum setup time t_{su(SDDV-SDCH)M0} and minimum hold time t_{h(SDCH-SDD)M0} with reference to the rising clock edge of the SDx_Cy signal in the SDFM module.

Figure 2-3 TMS320F28379D SDFM Timing Diagram – Mode 0

For the TMS320F28379D SDFM module in Mode 0, we recommend to use the SDFM operation with qualified GPIO (3-sample window). This mode provides protection against random noise glitches with the input clock signal (SDx_Cy) and data input (SDx_Dy) to avoid false comparator over-current trip and false Sinc filter output. The minimum setup and hold times for a 200 MHz system clock with TMD320F28379D are both 10 ns: t_{su (SDDV-SDCH)M0} (MIN) = 10 ns and t_{h(SDCH-SDD)M0} (MIN) = 10 ns.

This creates a design challenge as the AMC1306M25 minimum hold time t_h(MIN) is 3.5 ns, but 10 ns is required for the SDFM module to maintain correct acquisition at the data input SDx_Dy with reference to the rising clock edge of the SDx_Cy signal.

An additional challenge is that the propagation delay of additional components in the signal chain with the digital interface such as a clock buffer as well as the propagation delay of the clock and data signals introduced by the trace length on the PCB have an impact on the timings between SDx_Cy and SDx_Dy inputs and complicate the correct acquisition timing of the data input.

The same applies to Delta-Sigma modulators with a LVDS interface, such as the AMC1305L25. The only difference to AMC1306M25 Delta-Sigma modulators with CMOS interface type is that additional components like a LVDS driver and receiver are required with the digital signal chain to a MCU with CMOS interface, which contribute to further propagation delays. Figure 2-4 shows a simplified digital interface between the isolated Delta-Sigma modulator AMC1305L25 with LVDS interface and the MCU TMS320F28379D with CMOS interface.

Figure 2-4 AMC1305L25 Digital Interface to TMS320F28379D

Figure 2-5 shows a simplified digital interface of an isolated Delta-Sigma modulator with internally-created clock source AMC1303Mx with CMOS interface to TMS320F28379D with CMOS interface. The internally generated clock signal CLKOUT of the AMC1303Mx is input to the MCUs Sigma-Delta Filter Module (SDFM) SD1_C1 (GPIO123). The isolated data output DOUT of the Delta-Sigma Modulator is directly connected to MCUs data input SD1_D1 (GPIO122) of the SDFM.

Figure 2-5 AMC1303M2520 3.3-V CMOS Digital Interface to TMS320F28379D

When using an isolated modulator with an internal clock, the digital interface challenge is limited to the different timing specifications of the isolated Delta-Sigma modulator and the MCUs setup and hold times. The propagation delay of clock and data signals introduced by the trace length on the PCB can be neglected if the clock and data signals are routed at the same length. Typically, the modulator is directly interfaced to the MCU and there’s no need for a buffer or level-shifter, which adds additional propagation delay.

The AMC1303Mx hold time t_h(MIN) is 7 ns and the delay time t_d (MAX) is 15 ns for the 10 MHz and 20 MHz clock versions. The challenge is that the AMC1303Mx minimum hold t_h(MIN) is 7 ns, but 10 ns is required by the SDFM module for correct acquisition of the data input at SDx_Dy without any setup and hold time violations.

For isolated Delta-Sigma modulators with a Manchester encoded bitstream output, e.g. AMC1306E25, data and clock are transferred through a single-wire. So that the setup and hold time requirements of the receiving device versus the modulator clock do not have to be considered.

A commonly used method and compromise to meet the MCUs setup and hold time requirements is to reduce the clock frequency. However, reducing the clock frequency is also reducing the data output rate of the isolated Delta-Sigma modulator and increases the latency of the current measurement. A more suitable method is to use clock edge delay compensation which enables moving the clock edge of the clock signal to an ideal sample point of the data signal to meet the setup and hold timing requirements. By using this method, the clock frequency limitations are eliminated which allows the isolated Delta-Sigma modulator and the system to operate at full performance.

To meet and further optimize the MCUs setup and hold timing requirements for reliable data acquisition, clock edge delay compensation is recommended. Clock edge delay compensation can be implemented by various methods, summarized below and expanded upon in the following section:

1. Additional clock signal with software configurable phase delay
2. Clock signal with hardware configurable phase delay
3. Clock return
4. Clock inversion at MCU

Figure 3-1 shows the first compensation method, where an additional phase locked clock signal with a software configurable phase delay is used. For this compensation method the phase-shifted clock signal CLKOUT_delay is used as the clock input to SD0_CLK of the Sigma-Delta Filter Module (SDFM). For other types of Delta-Sigma Modulators and MCUs e.g. C2000 MCUs, the compensation method follows the same principle.

Figure 3-1 AMC1306M25 to AM243x MCU Interface With Software Configurable Clock Phase Delay

The implementation of a second phase-shifted clock signal offers the highest degree of freedom and user configurability. This means that various values for minimum hold time t_h(MIN) of various isolated modulators can be compensated by a simple change to the phase-shift value in software. The clock signals rising edge at the SD0_CLK input is phase-shifted such that the clocking signal complies with the data sampling point of the SDFM, as shown in Figure 3-2. The AM243x PRU_ICSSG PRU Timing Requirements in Sigma Delta Mode are 10 ns for minimum setup time t_{su (SD_D-SD_CLK)} (MIN) = 10 ns and 5 ns for minimum hold time t_{h(SD_CLK-SD_D)} (MIN) = 5 ns. This creates a need for compensation to maintain correct acquisition at the data input SDx_D with reference to the rising clock edge of the SDx_CLK signal as the AMC1306M25 minimum hold time t_h(MIN) is 3.5 ns, but 5 ns can be required. After this compensation method is applied, the 10-ns minimum setup and 5-ns hold timings for the Sigma Delta Mode of the AM243x PRU_ICSSG PRU timing requirements are met, see Figure 3-2.

Figure 3-2 AM243x SDFM Timing With 30-ns Phase-Shifted Clock Signal Input at SD0_CLK (GPIO1_1)

Clock signal compensation with hardware configurable phase delay of the digital interface between AMC1306M25 and MCU is shown in Figure 3-3. With this compensation method a phase-shifted clock signal by a phase delay in hardware is connected to the clock input SDFM_CLKIN of the SDFM module of the MCU. This type of compensation works for any MCU with Sigma-Delta Filter Module, but is only recommended for isolated Delta-Sigma Modulator’s with an external clock source and CMOS interface.

Figure 3-3 AMC1306M25 Digital Interface to MCU With Compensation by Hardware Configurable Phase Delay

To implement a phase delay in hardware, a logic gate or buffer can be used to introduce a propagation delay in the clock signal. However, when implementing a delay in hardware the value of the delay is strongly dependent on the propagation delay of the hardware block limiting the degree of freedom and user configurability. The working principle of the compensation by clock signal with hardware configurable phase delay follows the same principle described in Section 3.1.