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CDCEL949

ACTIVE

Programmable 4-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs

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Data sheet

CDCEL949

ACTIVE
Data sheet Order now

Product details

Function Clock synthesizer Number of outputs 9 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL Output type LVCMOS Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Function Clock synthesizer Number of outputs 9 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL Output type LVCMOS Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Member of programmable clock generator family
    • CDCEx913: 1 PLLs, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-System programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLLs, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-System programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. These devices generate up to nine output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCEx949 operates in a 1.8V environment within a temperature range of –40°C to 85°C.

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. These devices generate up to nine output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCEx949 operates in a 1.8V environment within a temperature range of –40°C to 85°C.
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Technical documentation

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Type Title Date
* Data sheet CDCE(L)949: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. G) PDF | HTML 16 Jan 2024
Application note VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 23 Apr 2012
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 22 Nov 2010
User guide CDCE(L)9xx Performance Evaluation Module (Rev. A) 07 Jul 2010
Application note Troubleshooting I2C Bus Protocol 19 Oct 2009
Application note Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 23 Sep 2009
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual 09 Dec 2008
Application note Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 31 Mar 2008
Application note Practical consideration on choosing a crystal for CDCE(L)9xx family 24 Mar 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCEL949PERF-EVM — CDCEL949 Performance Evaluation Module

The CDCEL949PERF-EVM will help to verify the functionality and performance of CDCEL949 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items are included: The EVM use's guide : SCAU022; the (...)

User guide: PDF
Not available on TI.com
Evaluation board

CDCEL9XXPROGEVM — CDCE(L)949 Family EEPROM Programming Board

The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)

User guide: PDF
Not available on TI.com
Driver or library

SCAC131 — Drivers for the CDCEL9xx programmer EVM

Supported products & hardware

Supported products & hardware

Products
Clock generators
CDCE913 — Programmable 1-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE925 — Programmable 2-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE937 — Programmable 3-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE949 — Programmable 4-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCEL913 — Programmable 1-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL925 — Programmable 2-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL937 — Programmable 3-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL949 — Programmable 4-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs
Hardware development
Evaluation board
CDCE906-706PROGEVM — CDCE906 and CDCE706 programmable EVM CDCE925PERF-EVM — CDCE925 Performance Evaluation Module CDCE949PERF-EVM — CDCE949 Performance Evaluation Module CDCEL913PERF-EVM — CDCEL913 Performance Evaluation Module CDCEL925PERF-EVM — CDCEL925 Performance Evaluation Module CDCEL949PERF-EVM — CDCEL949 Performance Evaluation Module
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Support software

CLOCKPRO — ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

Supported products & hardware

Supported products & hardware

Products
Clock generators
CDCE706 — 300-MHz, LVCMOS, programmable 3-PLL clock synthesizer / multiplier / divider CDCE906 — 167-MHz, LVCMOS, programmable 3-PLL clock synthesizer / multiplier / divider CDCE913 — Programmable 1-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE925 — Programmable 2-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE937 — Programmable 3-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE949 — Programmable 4-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCEL913 — Programmable 1-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL925 — Programmable 2-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL937 — Programmable 3-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL949 — Programmable 4-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs
Hardware development
Evaluation board
CDCE906-706PROGEVM — CDCE906 and CDCE706 programmable EVM CDCE913PERF-EVM — CDCE913 Performance Evaluation Module CDCE925PERF-EVM — CDCE925 Performance Evaluation Module CDCE949PERF-EVM — CDCE949 Performance Evaluation Module CDCEL913PERF-EVM — CDCEL913 Performance Evaluation Module CDCEL925PERF-EVM — CDCEL925 Performance Evaluation Module CDCEL949PERF-EVM — CDCEL949 Performance Evaluation Module CDCEL9XXPROGEVM — CDCE(L)949 Family EEPROM Programming Board
Software
Software programming tool
CLOCKPRO — ClockPro™ Programming Software
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Support software

SCAC073 — TI-Pro-Clock Programming Software

Supported products & hardware

Supported products & hardware

Products
Clock generators
CDC706 — 200-MHz, LVCMOS, custom-programmed 3-PLL clock synthesizer, multiplier & divider CDC906 — 167-MHz, LVCMOS, custom-programmed 3-PLL clock synthesizer, multiplier & divider CDCE706 — 300-MHz, LVCMOS, programmable 3-PLL clock synthesizer / multiplier / divider CDCE906 — 167-MHz, LVCMOS, programmable 3-PLL clock synthesizer / multiplier / divider CDCE913 — Programmable 1-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE925 — Programmable 2-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE937 — Programmable 3-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCE949 — Programmable 4-PLL VCXO clock synthesizer with 2.5-V or 3.3-V LVCMOS outputs CDCEL913 — Programmable 1-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL925 — Programmable 2-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL937 — Programmable 3-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs CDCEL949 — Programmable 4-PLL VCXO clock synthesizer with 1.8-V LVCMOS outputs
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TSSOP (PW) 24 Ultra Librarian
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Ordering & quality

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  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

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