TCA6424

Name: TCA6424
Brand: TI
SKU: TCA6424
Price: 1.417 USD

NOT RECOMMENDED FOR NEW DESIGNS

24-bit translating 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, reset & config registers

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Data sheet

document-pdfAcrobat TCA6424 Low Voltage 24-Bit I2C and SMBus I/O Expander datasheet (Rev. B)

TCA6424 is not recommended for new designs

This product continues to be available for existing customers. New designs should consider an alternate product.

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TCA6424A

ACTIVE

24-bit translating 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, reset & config registers TCA6424A is an enhanced version of the TCA6424 with performance enhancements related to Interrupt and Reset.

TCA6424

NOT RECOMMENDED FOR NEW DESIGNS

Data sheet

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Product details

Number of I/Os

24

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Rating

Catalog

Frequency (max) (MHz)

0.4

Operating temperature range (°C)

-40 to 85

Number of I/Os

24

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Rating

Catalog

Frequency (max) (MHz)

0.4

Operating temperature range (°C)

-40 to 85

UQFN (RGJ)

32

25 mm² 5 x 5

Operating Power-Supply Voltage Range of 1.65 V to 5.5 V
Allows Bidirectional Voltage-Level Translation and GPIO Expansion Between:
- 1.8-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 2.5-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 3.3-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 5-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
I²C to Parallel Port Expander
Low Standby Current Consumption of 1 μA
Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the SCL and SDA Inputs
- V_hys = 0.18 V Typ at 1.8 V
- V_hys = 0.25 V Typ at 2.5 V
- V_hys = 0.33 V Typ at 3.3 V
- V_hys = 0.5 V Typ at 5 V
5-V Tolerant I/O Ports
Active-Low Reset (RESET) Input
Open-Drain Active-Low Interrupt (INT) Output
400-kHz Fast I²C Bus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power Up With All Channels Configured as Inputs
No Glitch On Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

Operating Power-Supply Voltage Range of 1.65 V to 5.5 V
Allows Bidirectional Voltage-Level Translation and GPIO Expansion Between:
- 1.8-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 2.5-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 3.3-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
- 5-V SCL/SDA and
  1.8-V, 2.5-V, 3.3-V, or 5-V P Port
I²C to Parallel Port Expander
Low Standby Current Consumption of 1 μA
Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the SCL and SDA Inputs
- V_hys = 0.18 V Typ at 1.8 V
- V_hys = 0.25 V Typ at 2.5 V
- V_hys = 0.33 V Typ at 3.3 V
- V_hys = 0.5 V Typ at 5 V
5-V Tolerant I/O Ports
Active-Low Reset (RESET) Input
Open-Drain Active-Low Interrupt (INT) Output
400-kHz Fast I²C Bus
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
Power Up With All Channels Configured as Inputs
No Glitch On Power Up
Noise Filter on SCL/SDA Inputs
Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

This 24-bit I/O expander for the two-line bidirectional bus (I²C) is designed to provide general-purpose remote I/O expansion for most microcontroller families via the I²C interface [serial clock (SCL) and serial data (SDA)].

The major benefit of this device is its wide V_CC range. It can operate from 1.65 V to 5.5 V on the P-port side and on the SDA/SCL side. This allows the TCA6424 to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs, remain at a 5-V power supply.

The bidirectional voltage level translation in the TCA6424 is provided through V_CCI. V_CCI should be connected to the V_CC of the external SCL/SDA lines. This indicates the V_CC level of the I²C bus to the TCA6424. The voltage level on the P-port of the TCA6424 is determined by the V_CCP.

The TCA6424 consists of three 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.

The system master can reset the TCA6424 in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I²C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The TCA6424 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I²C bus. Thus, the TCA6424 can remain a simple slave device.

The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I²C address and allow up to two devices to share the same I²C bus or SMBus.