ADS5483

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16 位、135MSPS 模数转换器 (ADC)

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数据表

document-pdfAcrobat 16-Bit, 80/105/135 MSPS High-Speed ADCs 数据表 (Rev. C) (英语)

ADS5483

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产品详情

Sample rate (max) (Msps)

135

Resolution (Bits)

16

Number of input channels

1

Interface type

Parallel LVDS

Analog input BW (MHz)

485

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

3

Power consumption (typ) (mW)

2100

Architecture

Pipeline

SNR (dB)

79

ENOB (Bits)

12.6

SFDR (dB)

97

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

135

Resolution (Bits)

16

Number of input channels

1

Interface type

Parallel LVDS

Analog input BW (MHz)

485

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

3

Power consumption (typ) (mW)

2100

Architecture

Pipeline

SNR (dB)

79

ENOB (Bits)

12.6

SFDR (dB)

97

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

80/105/135-MSPS Sample Rates
16-Bit Resolution
SFDR: 95 dBc at 70 MHz and 135 MSPS
SNR: 78.6 dBFS at 70 MHz and 135 MSPS
Efficient DDR LVDS-Compatible Outputs
Internal Dither Available
Total Power Dissipation: 2.2 W
Power-Down Mode: 70 mW
On-Chip High Impedance Analog Buffer
QFN-64 PowerPAD Package (9 mm × 9 mm Footprint)
Industrial Temperature Range: –40°C to +85°C
APPLICATIONS
- Wireless Infrastructure (Multi-Carrier GSM, WCDMA, LTE)
- Test and Measurement Instrumentation
- Software-Defined Radio
- Data Acquisition
- Power Amplifier Linearization
- Communication Instrumentation
- Radar
- Medical Imaging

All trademarks are the property of their respective owners.

80/105/135-MSPS Sample Rates
16-Bit Resolution
SFDR: 95 dBc at 70 MHz and 135 MSPS
SNR: 78.6 dBFS at 70 MHz and 135 MSPS
Efficient DDR LVDS-Compatible Outputs
Internal Dither Available
Total Power Dissipation: 2.2 W
Power-Down Mode: 70 mW
On-Chip High Impedance Analog Buffer
QFN-64 PowerPAD Package (9 mm × 9 mm Footprint)
Industrial Temperature Range: –40°C to +85°C
APPLICATIONS
- Wireless Infrastructure (Multi-Carrier GSM, WCDMA, LTE)
- Test and Measurement Instrumentation
- Software-Defined Radio
- Data Acquisition
- Power Amplifier Linearization
- Communication Instrumentation
- Radar
- Medical Imaging

All trademarks are the property of their respective owners.

The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that operate from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x integrated analog input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design.

Designed for highest total ENOB, the ADS548x family has outstanding low noise performance and spurious-free dynamic range.

The ADS548x is available in an QFN-64 PowerPAD package. The device is built on Texas Instruments complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to +85°C).

The ADS5481/ADS5482/ADS5483 (ADS548x) is a 16-bit family of analog-to-digital converters (ADCs) that operate from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. The ADS548x integrated analog input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design.

Designed for highest total ENOB, the ADS548x family has outstanding low noise performance and spurious-free dynamic range.

The ADS548x is available in an QFN-64 PowerPAD package. The device is built on Texas Instruments complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to +85°C).

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顶层文档	类型	标题	下载最新的英语版本	日期
*	数据表	16-Bit, 80/105/135 MSPS High-Speed ADCs 数据表 (Rev. C)		2009-10-6
	模拟设计期刊	Q3 2009 Issue Analog Applications Journal		2018-9-24
	应用手册	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)		2015-5-22
	模拟设计期刊	Power-supply design for high-speed ADCs (Rev. A)		2015-5-18
	应用手册	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)		2013-7-19
	应用手册	High-Speed, Analog-to-Digital Converter Basics		2012-1-11
	应用手册	时钟抖动时域分析第 3 部分	英语版	2011-12-2
	模拟设计期刊	模拟应用期刊 2011 第三季度	英语版	2011-12-2
	模拟设计期刊	时钟抖动时域分析，第 2 部分	英语版	2011-4-5
	应用手册	Input Impedance Measurement Using ADC FFT Data		2011-1-11
	模拟设计期刊	4Q 2010 Issue Analog Applications Journal		2010-11-15
	应用手册	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)		2010-9-10
	模拟设计期刊	Impact of sampling-clock spurs on ADC performance		2009-7-14
	应用手册	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio		2009-4-28
	应用手册	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters		2008-6-8
	应用手册	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010		2008-6-2
	应用手册	QFN Layout Guidelines		2006-7-28

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