The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher speed serial links. This reference design helps customers reduce the number of serial links that need to be implemented and managed within an application. TLK10081 enables customers to aggregate and de-aggregate multiple serial links, of all types including raw data types. Also, featured is the CDCM6208 device that can provide extremely low-jitter Clock input to the TLK10081 in customer systems that do not have one available (or does not meet the jitter requirement of the system). The high-speed signals of channel A have been routed to SFP+ modules for easy evaluation in systems that implement optical fiber configurations. The high-speed signals of channel B have been routed to edge launch SMA connectors for easy evaluation in systems that use standard test equipment.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Test results for the reference design, including efficiency graphs, test prerequisites and more
Detailed schematic diagram for design layout and components
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| User guide | TIDA-00269 Quick Start Guide | Jul. 14, 2014 | ||
| Test report | TIDA-00269 Test Results | Jul. 14, 2014 |
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