The DRV7167A is a 100V
half-bridge power stage, with integrated gate-driver and enhancement-mode Gallium
Nitride (GaN) FETs. The device consist of two 100V GaN FETs driven by one
high-frequency GaN FET driver in a half-bridge configuration.
GaN FETs provide significant advantages for power
conversion as they have zero reverse recovery and very small input capacitance
CISS and output capacitance COSS. All the devices are
mounted on a completely bond-wire free package platform with minimized package
parasitic elements. The DRV7167A is available in 7.0mm × 4.5mm ×
0.89mm
lead-free
packages and can be easily mounted on
PCBs.
The TTL logic compatible inputs can support 3.3V
and 5V logic levels regardless of the GVDD voltage. A proprietary bootstrap voltage
regulation technique ensures the gate voltages of the enhancement mode GaN FETs are
within a safe operating range. The device supports turn-on and turn-off slew-rate
control for both FETs, single PWM mode for use with IO-limited controllers,
short-circuit protection (SCP) , Over-Temperature Detection (OTD) and zero-voltage
detection (ZVD) reporting
to minimize third quandrant condution time.
The device extends advantages of discrete GaN FETs
by offering a more user-friendly interface. It is an ideal solution for applications
requiring high-frequency, high-efficiency operation in a small form factor.
The DRV7167A is a 100V
half-bridge power stage, with integrated gate-driver and enhancement-mode Gallium
Nitride (GaN) FETs. The device consist of two 100V GaN FETs driven by one
high-frequency GaN FET driver in a half-bridge configuration.
GaN FETs provide significant advantages for power
conversion as they have zero reverse recovery and very small input capacitance
CISS and output capacitance COSS. All the devices are
mounted on a completely bond-wire free package platform with minimized package
parasitic elements. The DRV7167A is available in 7.0mm × 4.5mm ×
0.89mm
lead-free
packages and can be easily mounted on
PCBs.
The TTL logic compatible inputs can support 3.3V
and 5V logic levels regardless of the GVDD voltage. A proprietary bootstrap voltage
regulation technique ensures the gate voltages of the enhancement mode GaN FETs are
within a safe operating range. The device supports turn-on and turn-off slew-rate
control for both FETs, single PWM mode for use with IO-limited controllers,
short-circuit protection (SCP) , Over-Temperature Detection (OTD) and zero-voltage
detection (ZVD) reporting
to minimize third quandrant condution time.
The device extends advantages of discrete GaN FETs
by offering a more user-friendly interface. It is an ideal solution for applications
requiring high-frequency, high-efficiency operation in a small form factor.