The SN74LV8T595-EP device contains an 8-bit, serial-in, parallel-out shift
register that feeds an 8-bit D-type storage register. The storage register has
parallel 3-state outputs. Separate clocks are provided for both the shift and
storage register. The shift register has a direct overriding clear (
SRCLR) input, serial (SER) input, and a serial output
(QH) for cascading. When the output-enable (
OE) input is high, the outputs are in a high-impedance state.
Internal register data is not impacted by the operation of the
OE input. The output level is referenced to the supply
voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower
threshold circuit to support up translation for lower voltage CMOS inputs (for
example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the
5V tolerant input pins enable down translation (for example, 3.3V to 2.5V
output).
The SN74LV8T595-EP device contains an 8-bit, serial-in, parallel-out shift
register that feeds an 8-bit D-type storage register. The storage register has
parallel 3-state outputs. Separate clocks are provided for both the shift and
storage register. The shift register has a direct overriding clear (
SRCLR) input, serial (SER) input, and a serial output
(QH) for cascading. When the output-enable (
OE) input is high, the outputs are in a high-impedance state.
Internal register data is not impacted by the operation of the
OE input. The output level is referenced to the supply
voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower
threshold circuit to support up translation for lower voltage CMOS inputs (for
example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the
5V tolerant input pins enable down translation (for example, 3.3V to 2.5V
output).