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Noninverting buffers & drivers

SN74LVC126A

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Four-channel, 1.65V to 3.6V buffers with three-state outputs

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Data sheet

SN74LVC126A

ACTIVE
Data sheet Order now

Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4 VQFN (RGY) 14 12.25 mm² 3.5 x 3.5 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to +125°C
  • Inputs accept voltages up to 5.5V
  • Maximum tpd of 4.7ns at 3.3V
  • Typical VOLP (output ground bounce), <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot), >2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to +125°C
  • Inputs accept voltages up to 5.5V
  • Maximum tpd of 4.7ns at 3.3V
  • Typical VOLP (output ground bounce), <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot), >2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17

The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation.

The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.

The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation.

The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. U) PDF | HTML 29 Jul 2024
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Design guide 18-V/400-W 98% Efficient Compact Brushless DC Motor Drive Design Guide 23 Aug 2016
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74LVC126A Behavioral SPICE Model

SCAM110.ZIP (7 KB) - PSpice Model
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Simulation model

SN74LVC126A IBIS Model (Rev. C)

SCEM014C.ZIP (45 KB) - IBIS Model
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Reference designs

TIDA-01606 — 11-kW, bidirectional three-phase three-level (T-type) inverter and PFC reference design

This reference design provides an overview on how to implement a bidirectional three-level, three-phase, SiC-based active front end (AFE) inverter and power factor correction (PFC) stage. The design uses switching frequency up to 90kHz and an LCL output filter to reduce the size of the magnetics. (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00771 — 10.8V/250W, 97% Efficient,Compact Brushless DC Motor Drive w/Stall Current Limit Reference Design

The TIDA-00771 is a 20 A RMS drive for a three phase brushless DC (BLDC) motor in power tools operating from a 3-cell Li-ion battery with a voltage range of 5 V to 12.6 V. This design is a 45 x 50 mm compact drive implementing sensor-based trapezoidal control. The design uses a discrete, compact (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00772 — 18-V/400-W 98% Efficient Compact Brushless DC Motor Drive w/Stall Current Limit Reference Design

The TIDA-00772 is a 18 A RMS drive for a three phase brushless DC (BLDC) motor in power tools operating from a 5-cell Li-ion battery with a voltage up to 21 V. This design is a 45 x 50 mm compact drive implementing sensor-based trapezoidal control. The design uses a discrete, compact MOSFET-based (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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