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SN74LVC1G17

ACTIVE

Single 1.65-V to 5.5-V buffer with Schmitt-Trigger inputs

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Data sheet

SN74LVC1G17

ACTIVE
Data sheet Order now

Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 DSBGA (YZV) 4 1.5625 mm² 1.25 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in Ultra Small 0.64-mm2 Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G17 device contains one buffer and performs the Boolean function Y = A.

The CMOS device has high output drive while maintaining low static power dissipation over a broad Vcc operating range.

The SN74LVC1G17 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8mm.

This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G17 device contains one buffer and performs the Boolean function Y = A.

The CMOS device has high output drive while maintaining low static power dissipation over a broad Vcc operating range.

The SN74LVC1G17 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8mm.
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Technical documentation

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Type Title Date
* Data sheet SN74LVC1G17 Single Schmitt-Trigger Buffer datasheet (Rev. W) PDF | HTML 21 Sep 2020
Product overview Generate a Power-On Reset Pulse PDF | HTML 14 Jun 2023
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application brief Debounce a Switch PDF | HTML 08 Oct 2020
Application brief Generate a Clock Signal from a Crystal Oscillator PDF | HTML 08 Oct 2020
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 May 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note Designing and Manufacturing with TI's X2SON Packages 23 Aug 2017
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

HSPICE Model for SN74LVC1G17

SCEJ260.ZIP (88 KB) - HSpice Model
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Simulation model

SN74LVC1G17 Behavioral SPICE Model

SCEM635.ZIP (7 KB) - PSpice Model
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Simulation model

SN74LVC1G17 IBIS Model (Rev. C)

SCEM299C.ZIP (45 KB) - IBIS Model
Download

Many TI reference designs include the SN74LVC1G17

Use our reference design selection tool to review and identify designs that best match your application and parameters.

View reference designs
Package Pins CAD symbols, footprints & 3D models
DSBGA (YZP) 5 Ultra Librarian
DSBGA (YZV) 4 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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