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TMS320C6474

ACTIVE

Multicore Digital Signal Processor

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Data sheet
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TMS320C6474

ACTIVE
Data sheet Order now

Product details

CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 95
CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 95
FCBGA (CUN) 561 529 mm² 23 x 23
  • Key Features
    • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
    • Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
    • Commercial Temperature and Extended Tmperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module non-UMTS Systems
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time:
      • 1.2-GHz Device: 1.0-ns to 0.83-ns
      • 1-GHz Device: 1-ns
      • 850-MHz Device: 1.18 ns
    • Clock Rate:
      • 1.2-GHz Device: 1-GHz to 1.2-GHz
      • 1-GHz Device: 1-GHz
      • 850-MHz Device: 850 MHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature:
      • 1.2-GHz Device: 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
      • 850-MHZ and 1-GHz Device: 0°C to 100°C
    • Extended Temperature:
      • 1.2-GHz Device: -40°C to 95°C(1)
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 512 K-Bit (64 K-Byte) L3 ROM
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.
  • Key Features
    • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
    • Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
    • Commercial Temperature and Extended Tmperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module non-UMTS Systems
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time:
      • 1.2-GHz Device: 1.0-ns to 0.83-ns
      • 1-GHz Device: 1-ns
      • 850-MHz Device: 1.18 ns
    • Clock Rate:
      • 1.2-GHz Device: 1-GHz to 1.2-GHz
      • 1-GHz Device: 1-GHz
      • 850-MHz Device: 850 MHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature:
      • 1.2-GHz Device: 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
      • 850-MHZ and 1-GHz Device: 0°C to 100°C
    • Extended Temperature:
      • 1.2-GHz Device: -40°C to 95°C(1)
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 512 K-Bit (64 K-Byte) L3 ROM
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.
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This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

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Type Title Date
* Data sheet TMS320C6474 Multicore Digital Signal Processor Data Manual datasheet (Rev. H) 11 Apr 2011
* Errata TMS320C6474 DSP Silicon Errata (Silicon Revisions 2.1, 1.3, 1.2) (Rev. C) 11 Mar 2011
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 May 2021
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
Application note Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 19 Jul 2013
More literature Picture it: DSPs in medical imaging (Rev. C) 12 Jul 2013
Application note Multicore Programming Guide (Rev. B) 29 Aug 2012
User guide TMS320C6474 DSP EMAC/MDIO Module Reference Guide (Rev. B) 02 Mar 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide TMS320C6474 DSP Enhanced DMA (EDMA3) Controller User's Guide (Rev. B) 01 Jul 2011
User guide Bootloader User's Guide for the TMS320C645x/C647x DSP (Rev. G) 03 Jun 2011
User guide TMS320C6474 DSP DDR2 Memory Controller User's Guide (Rev. D) 02 Jun 2011
Application note Tuning VCP2 and TCP2 Bit Error Rate Performance 11 Feb 2011
User guide TMS320C6474 Serial RapidIO (SRIO) User's Guide (Rev. D) 03 Feb 2011
Application note TMS320C6474 Hardware Design Guide (Rev. B) 03 Aug 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
User guide TMS320C6474 DSP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. A) 18 May 2010
User guide TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 Reference Guide (Rev. B) 08 Dec 2009
User guide TMS320C6474 DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. A) 28 Oct 2009
Application note Connecting Antenna Interface (AIF) With TDM Bridge Chip (IDT 80HFC001) 28 Aug 2009
Application note Direct I/O Library 28 Aug 2009
Application note Using the TMS320C6474 Antenna Interface (AIF) for Inter-DSP Communication 28 Aug 2009
Application note TMS320C6474 DDR2 Implementation Guidelines (Rev. A) 04 Aug 2009
Application note How to Approach Inter-Core Communication on TMS320C6474 27 Jan 2009
Application note Inter-Core Communication on TMS320C6474 12 Jan 2009
Application note TPS40197 Reference Design 17 Dec 2008
White paper See the difference:DSPs in medical imaging 31 Oct 2008
Application note Migrating from TMS320C6455 to TMS320C6474 14 Oct 2008
Application note TMS320C6474 Power Consumption Summary 14 Oct 2008
User guide TMS320C6474 Antenna Interface User's Guide 14 Oct 2008
Application note TMS320C6474 Common Bus Architecture (CBA) Throughput 14 Oct 2008
User guide TMS320C6474 DSP 64-Bit Timer User's Guide 14 Oct 2008
User guide TMS320C6474 DSP Chip Interrupt Controller (CIC) User's Guide 14 Oct 2008
User guide TMS320C6474 DSP General-Purpose Input/Output (GPIO) User's Guide 14 Oct 2008
User guide TMS320C6474 DSP Power/Sleep Controller (PSC) User’s Guide 14 Oct 2008
User guide TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL) Controller UG 14 Oct 2008
User guide TMS320C6474 DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide 14 Oct 2008
User guide TMS320C6474 Frame Synchronization User's Guide 14 Oct 2008
Application note TMS320C6474 Module Throughput Application Report 14 Oct 2008
Application note TMS320C6474 Multicore Digital Signal Processor Technical Brief 14 Oct 2008
Application note TMS320C6474 SERDES Implementation Guidelines 14 Oct 2008
User guide TMS320C6474 Semaphore User's Guide 14 Oct 2008
Application note C6474 (x4) Power Using Modules 01 Oct 2008
Application note C6474 (x2) Power Using Modules 30 Sep 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 Aug 2008
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 Oct 2005
User guide High-Speed DSP Systems Design Reference Guide 20 May 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. For the majority of devices it is recommended to use the newer, lower cost XDS110 (www.ti.com/tool/TMDSEMU110-U). The XDS200 supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. All XDS (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Debug probe

LB-3P-TRACE32-DSP — Lauterbach TRACE32 Debug and Trace System for Digital Signal Processors (DSPs)

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

From: Lauterbach GmbH
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Software development kit (SDK)

LINUXMCSDK — Linux MCSDK for C66x, C647x and C645x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

Supported products & hardware

Supported products & hardware

Products
Audio & radar DSP SoCs
  • TMS320C6455 — C64x+ fixed-point DSP up to 1.2GHz, 64-bit EMIFA, 32- and 16-bit DDR2, 1Gbps Ethernet
  • TMS320C6457 — Communications infrastructure digital signal processor
  • TMS320C6678 — High performance octo-core C66x fixed and floating-point DSP- up to 1.25GHz
Multimedia & industrial networking SoCs
  • TMS320C6472 — Fixed-Point Digital Signal Processor
  • TMS320C6474 — Multicore Digital Signal Processor
  • TMS320C6670 — 4 core fixed and floating point DSP for Communications and Telecom
Hardware development
Evaluation board
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Software development kit (SDK)

MEDIMGSTK-C66X — TI Embedded Processor Software Tool Kit for Medical Imaging (STK-MED) - for C66x and C64x+ based processors

The TI Embedded Processor Software Toolkit for Medical Imaging (STK-MED) is a collection of several standard ultrasound and optical coherence tomography (OCT) algorithms for TI’s C66x™ and C64x+™ architecture. The algorithms showcase how medical imaging functions can leverage the C66x and (...)
Supported products & hardware

Supported products & hardware

Products
Audio & radar DSP SoCs
  • DM505 — SoC for vision analytics 15mm package
  • SM320C6678-HIREL — High reliability product high performance 8-core C6678 fixed and floating-point DSP
  • TMS320C6454 — C64x+ fixed point DSP- up to 1GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps Ethernet
  • TMS320C6455 — C64x+ fixed-point DSP up to 1.2GHz, 64-bit EMIFA, 32- and 16-bit DDR2, 1Gbps Ethernet
  • TMS320C6457 — Communications infrastructure digital signal processor
Multimedia & industrial networking SoCs
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Driver or library

NDKTCPIP — TI-RTOS Networking

TI-RTOS Networking (formerly known as the NDK or Network Developers Kit) combines dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCUs as a part of TI-RTOS and also for high-performance TMS320C6000™ DSP-based devices.
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Driver or library

SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

Supported products & hardware

Supported products & hardware

Products
Audio & radar DSP SoCs
  • SM320C6201-EP — Enhanced product C6201 fixed point DSP
  • SM320C6455-EP — Enhanced product C6455 fixed point DSP
  • SMJ320C6201B — Fixed Point Digital Signal Processor, Military
  • SMJ320C6203 — Military grade C62x fixed point DSP - ceramic package
  • TMS320C6202B — C62x fixed point DSP- up to 300MHz, 384KB
  • TMS320C6203B — C62x fixed point DSP- up to 300MHz, 896KB
  • TMS320C6204 — Fixed-Point Digital Signal Processor
  • TMS320C6205 — Fixed-Point Digital Signal Processor
  • TMS320C6211B — C62x fixed point DSP- up to 167MHz
  • TMS320C6412 — C64x fixed point DSP- up to 720MHz, McBSP, McASP, I2cC, Ethernet
  • TMS320C6414 — C64x fixed point DSP- up to 720MHz, McBSP
  • TMS320C6414T — C64x fixed point DSP- up to 1GHz, McBSP
  • TMS320C6415 — C64x fixed point DSP- up to 720MHz, McBSP, PCI
  • TMS320C6415T — C64x fixed point DSP- up to 850MHz, McBSP, PCI
  • TMS320C6416 — C64x fixed point DSP- up to 720MHz, McBSP, PCI, VCP/TCP
  • TMS320C6416T — C64x fixed point DSP- up to 850MHz, McBSP, PCI, VCP/TCP
  • TMS320C6421 — C64x+ fixed point DSP- up to 600MHz, 8 Bit EMIFA , 16-Bit DDR2, SDRAM
  • TMS320C6421Q — C64x+ fixed point DSP- up to 600MHz, 8 Bit EMIFA, 16-Bit DDR2
  • TMS320C6424 — C64x+ fixed point DSP- up to 600MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2, SDRAM
  • TMS320C6424Q — C64x+ fixed point DSP- up to 600MHz, 16/8-Bit EMIFA, 32/16 Bit DDR2
  • TMS320C6452 — C64x+ fixed point DSP- up to 900MHz, 1Gbps Ethernet
  • TMS320C6454 — C64x+ fixed point DSP- up to 1GHz, 64-Bit EMIFA, 32/16 Bit DDR2, 1 Gbps Ethernet
  • TMS320C6455 — C64x+ fixed-point DSP up to 1.2GHz, 64-bit EMIFA, 32- and 16-bit DDR2, 1Gbps Ethernet
  • TMS320C6457 — Communications infrastructure digital signal processor
Multimedia & industrial networking SoCs
Automotive driver assist SoCs
  • TMS320DM642Q — Video/imaging fixed-point digital signal processor
  • TMS320DM6431Q — Digital media processor, up to 2400 MIPS, 300 MHz clock rate
  • TMS320DM6435Q — Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 1 McBSP
  • TMS320DM6437Q — Digital media processor, up to 4800 MIPS, 600 MHz clock rate, 1 McASP, 2 McBSP
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Driver or library

SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
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Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
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Driver or library

SPRC542 — C64x+ IQMath Library - A Virtual Floating Point Engine

Texas Instruments TMS320C64x+ IQmath Library is collection of highly optimized and high precision mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed point code on TMS320C64x+ devices. These routines are typically used in computationally (...)
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Driver or library

SPRC975 — TMS320C6474 Chip Support Library

This v3 release of CSL for TMS320C6474 contains peripheral programming (functional and register level) APIs for C6474 modules. The list of modules supported in this release is listed in the Release Notes, included in the download installer. This set of APIs provides peripheral abstraction that can (...)
Supported products & hardware

Supported products & hardware

Products
Multimedia & industrial networking SoCs
Download
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.
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Software codec

ADT-3P-DSPVOIPCODECS — Adaptive Digital Technologies DSP VOIP, speech and audio codecs

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)
From: Adaptive Digital Technologies, Inc.
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Software codec

C64XPLUSCODECS — CODECS - Video and Speech- C64x+-based Devices (OMAP35x, C645x, C647x, DM646, DM644x, DM643x)

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on (...)
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Simulation model

C6474 ZUN BSDL Model

SPRM335.ZIP (7 KB) - BSDL Model
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Simulation model

C6474 ZUN IBIS Model (Rev. A)

SPRM336A.ZIP (516 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
FCBGA (CUN) 561 Ultra Librarian
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