OMAP3515

Name: OMAP3515
Brand: TI
SKU: OMAP3515
Price: 35.428 USD

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Sitara 处理器：Arm Cortex-A8、3D 图形、LPDDR

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数据表

document-pdfAcrobat OMAP3515 and OMAP3503 Applications Processors 数据表 (Rev. H) (英语)

用户指南

document-pdfAcrobat
OMAP35x Technical Reference Manual (Rev. Y) (英语)

勘误

document-pdfAcrobat
OMAP3530/25/15/03 Applications Processor Silicon Errata (Rev. F) (英语)

OMAP3515

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数据表

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产品详情

CPU

1 Arm Cortex-A8

Frequency (MHz)

720

Graphics acceleration

1 3D

Display type

1 LCD

Operating system

Linux, RTOS

Security

Cryptographic acceleration

Rating

Catalog

Power supply solution

TPS65921, TPS65950

Operating temperature range (°C)

-40 to 105

CPU

1 Arm Cortex-A8

Frequency (MHz)

720

Graphics acceleration

1 3D

Display type

1 LCD

Operating system

Linux, RTOS

Security

Cryptographic acceleration

Rating

Catalog

Power supply solution

TPS65921, TPS65950

Operating temperature range (°C)

-40 to 105

FCCSP (CBB)

515

144 mm² 12 x 12

FCCSP (CUS)

423

256 mm² 16 x 16

OMAP3 Devices:
- OMAP™ 3 Architecture
- MPU Subsystem
  - Up to 720-MHz ARM® Cortex™-A8 Core
  - NEON™ SIMD Coprocessor
- PowerVR® SGX™ Graphics Accelerator
  - Tile-Based Architecture Delivering up to 1 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Programmable High-Quality Image Anti-Aliasing
- Fully Software-Compatible with ARM9™
- Commercial and Extended Temperature Grades
ARM Cortex-A8 Core
- ARMv7 Architecture
  - TrustZone®
  - Thumb®-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle® RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
ARM Cortex-A8 Memory Architecture:
- -KB Instruction Cache (4-Way Set-Associative)
- -KB Data Cache (4-Way Set-Associative)
- -KB L2 Cache
112KB of ROM
64KB of Shared SRAM
Endianess:
- ARM Instructions – Little Endian
- ARM Data – Configurable
External Memory Interfaces:
- General Purpose Memory Controller (GPMC)
  - 16-Bit-Wide Multiplexed Address and Data Bus
  - Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
  - Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
Camera Image Signal Processor (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
- Glueless Interface to Common Video Decoders
- Resize Engine
  - Resize Images From 1/4x to 4x
  - Separate Horizontal and Vertical Control
Display Subsystem
- Parallel Digital Output
  - Up to 24-Bit RGB
  - HD Maximum Resolution
  - Supports Up to 2 LCD Panels
  - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
  - Composite NTSC and PAL Video
  - Luma and Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
  - 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
  - 5-KB Transmit and Receive Buffer (McBSP2)
  - SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
  - Direct Interface to I2S and PCM Device and TDM Buses
  - 128-Channel Transmit and Receive Mode
- Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
- High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
- High-, Full-, and Low-Speed Multiport USB Host Subsystem
  - 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
- One HDQ™/1-Wire® Interface
- UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master and Slave High-Speed Inter-Integrated Circuit (I²C) Controllers
Removable Media Interfaces:
- Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock Management
- SmartReflex™ Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
Test Interfaces
- IEEE 1149.1 (JTAG) Boundary-Scan Compatible
- ETM Interface
- Serial Data Transport Interface (SDTI)
12 32-Bit General-Purpose Timers
2 32-Bit Watchdog Timers
1 32-Bit 32-kHz Sync Timer
Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
5-nm CMOS Technologies
Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
Discrete Memory Interface
Packages:
1.8-V I/O and 3.0-V (MMC1 Only),

Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

OMAP3 Devices:
- OMAP™ 3 Architecture
- MPU Subsystem
  - Up to 720-MHz ARM® Cortex™-A8 Core
  - NEON™ SIMD Coprocessor
- PowerVR® SGX™ Graphics Accelerator
  - Tile-Based Architecture Delivering up to 1 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Programmable High-Quality Image Anti-Aliasing
- Fully Software-Compatible with ARM9™
- Commercial and Extended Temperature Grades
ARM Cortex-A8 Core
- ARMv7 Architecture
  - TrustZone®
  - Thumb®-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle® RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
ARM Cortex-A8 Memory Architecture:
- -KB Instruction Cache (4-Way Set-Associative)
- -KB Data Cache (4-Way Set-Associative)
- -KB L2 Cache
112KB of ROM
64KB of Shared SRAM
Endianess:
- ARM Instructions – Little Endian
- ARM Data – Configurable
External Memory Interfaces:
- General Purpose Memory Controller (GPMC)
  - 16-Bit-Wide Multiplexed Address and Data Bus
  - Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
  - Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
Camera Image Signal Processor (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
- Glueless Interface to Common Video Decoders
- Resize Engine
  - Resize Images From 1/4x to 4x
  - Separate Horizontal and Vertical Control
Display Subsystem
- Parallel Digital Output
  - Up to 24-Bit RGB
  - HD Maximum Resolution
  - Supports Up to 2 LCD Panels
  - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
  - Composite NTSC and PAL Video
  - Luma and Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
  - 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
  - 5-KB Transmit and Receive Buffer (McBSP2)
  - SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
  - Direct Interface to I2S and PCM Device and TDM Buses
  - 128-Channel Transmit and Receive Mode
- Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
- High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
- High-, Full-, and Low-Speed Multiport USB Host Subsystem
  - 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
- One HDQ™/1-Wire® Interface
- UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master and Slave High-Speed Inter-Integrated Circuit (I²C) Controllers
Removable Media Interfaces:
- Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock Management
- SmartReflex™ Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
Test Interfaces
- IEEE 1149.1 (JTAG) Boundary-Scan Compatible
- ETM Interface
- Serial Data Transport Interface (SDTI)
12 32-Bit General-Purpose Timers
2 32-Bit Watchdog Timers
1 32-Bit 32-kHz Sync Timer
Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
5-nm CMOS Technologies
Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
Discrete Memory Interface
Packages:
1.8-V I/O and 3.0-V (MMC1 Only),

Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

Streaming video
Video conferencing
High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

Linux®
Windows® CE
Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:

Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
Section 4: Clock Specifications input and output clocks, DPLL and DLL
Section 5: Video Dac Specifications
Section 6: Timing Requirements and Switching Characteristics
Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

Streaming video
Video conferencing
High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

Linux®
Windows® CE
Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
Section 4: Clock Specifications input and output clocks, DPLL and DLL
Section 5: Video Dac Specifications
Section 6: Timing Requirements and Switching Characteristics
Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

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顶层文档	类型	标题	格式选项	日期
*	数据表	OMAP3515 and OMAP3503 Applications Processors 数据表 (Rev. H)		2013年 10月 10日
*	勘误表	OMAP3530/25/15/03 Applications Processor Silicon Errata (Rev. F)		2010年 10月 12日
*	用户指南	OMAP35x Technical Reference Manual (Rev. Y)		2012年 12月 19日
	用户指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020年 6月 1日
	应用手册	(Cancelled - see the B revision, create by mistake 14-may-2009) (Rev. C)	PDF \| HTML	2020年 3月 3日
	应用手册	OMAP3530/25/15/03, DM3730/25, AM3715/03 CBB, CBC and CUS reflow profiles		2019年 3月 20日
	用户指南	How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS		2018年 9月 24日
	应用手册	PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II (Rev. A)		2013年 11月 1日
	用户指南	Delta for OMAP35x Technical Reference Manual Version X to Version Y (Rev. Y)		2012年 12月 10日
	应用手册	使用 TPS65023 为 OMAP™3 供电：设计指南 (Rev. B)		2010年 10月 8日
	应用手册	PCB Assembly Guidelines for 0.5mm Package-on-Package Apps Processors, Part II		2010年 6月 23日
	应用手册	PCB Design Guidelines for 0.5mm Package-On-Package Apps Processors, Part I		2010年 6月 23日
	应用手册	Migrating from OMAP3530 to AM37x		2010年 6月 3日
	应用手册	Migrating from OMAP3530 to AM35x		2010年 5月 24日
	用户指南	OMAP35x Peripherals Overview Reference Guide (Rev. A)		2010年 1月 20日
	应用手册	OMAP35x Linux PSP Data Sheet		2009年 10月 16日
	设计指南	Powering OMAP35x with TPS65073x		2009年 10月 13日
	应用手册	Powering OMAP™3 With TPS6235x: Design-In Guide		2008年 12月 3日
	应用手册	OMAP35x 0.65mm Pitch Layout Methods (Rev. B)		2008年 6月 26日

设计与开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

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XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。对于大多数器件，建议使用较新、成本较低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 在单个仓体中支持更广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。

XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 引脚的多个适配器）连接到目标板，并通过 USB2.0 高速 (...)

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XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意，它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪，需要 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (480Mbps) (...)

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XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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软件开发套件 (SDK)

ANDROIDSDK-SITARA — 适用于 Sitara 微处理器的 Android 开发套件

虽然起初专为移动手持终端而设计，Android 操作系统仍允许嵌入式应用的设计人员轻松为产品增加高级操作系统。与 Google 联合开发的 Android 是一套可立即实现集成和生产的全面操作系统。

Android 操作系统的亮点包括：

完整的开放源码软件解决方案
基于 Linux
针对商业开发的简洁许可条款 (Apache)
包含一个完整的应用程序框架
允许通过 Java 轻松集成客户开发的应用程序
开箱即用的多媒体、图形和图形用户界面
如今已形成庞大的 Android 和应用程序开发人员社区

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软件开发套件 (SDK)

LINUXDVSDK-OMAP3530 — 用于 OMAP3530/3525 数字媒体处理器的 Linux 数字视频软件开发套件 (DVSDK)

The Linux Digital Video Software Development Kit (DVSDK) enables OMAP35x system integrators to quickly develop Linux-based multimedia applications that can be easily ported across different devices in the OMAP35x generation, including OMAP3530 and OMAP3525 application processors. The DVSDK combines (...)

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IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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软件编解码器

C64XPLUSCODECS — 编解码器 - 视频和语音 - 基于 C64x+ 的器件（OMAP35x、C645x、C647x、DM646、DM644x 和 DM643x）

TI 编解码器免费提供，附带生产许可且现在可供下载。所有编解码器均经过生产环境测试，可轻松集成到视频和语音应用中。点击“获取软件”按钮（上方），获取经过测试的最新编解码器版本。该页面及每个安装程序中都包含有数据表和发布说明。

其他信息：

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软件编解码器

OMAP35XCODECS — 用于 OMAP35x 的编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

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软件编程工具

FLASHTOOL — 用于 AM35x、AM37x、DM37x 和 OMAP35x 器件的 FlashTool

Flash Tool is a Windows-based application that can be used to transfer binary images from a host PC to TI Sitara AM35x, AM37x, DM37x and OMAP35x target platforms.

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