TPS537G4S
- Input voltage range: 4.5V to 17V
- Output voltage range: 0.25V to 5.5V
- PWMVID, AVSBus 1.4 and PMBus Interfaces
- Nvidia OVR16 spec compliant
- Dual output with 16 phases, flexible phase order assignment, and up to 4x native phase stacking
- Enhanced dual-edge D-CAP+ (DDCAP+) control loop to provide best-in-class transient performance with excellent dynamic current sharing
- Native trans-inductor voltage regulator (TLVR) topology support including open detect
- Optional PMBus secure device security Level 2 support from supply-chain to end-of-life protection
- Telemetry options with peak detection, time above programmable thresholds, and NVM storage
- Pin-selectable NVM configurations and PMBus address for reduced programming spins
- Individual phase current calibration and reporting
- PSI pin support for quick power state changes
- Fast phase-adding for undershoot reduction
- Fully compatible with TI power stages and power modules for high-density power delivery
- Patented AutoBalance™ phase current balancing
- Accurate, adjustable voltage positioning
- Selectable per-phase current limit
- Selectable current limit on total average current
- Analog IMON voltage output with programmable gain and offset options
- Frequency spread spectrum support
- Operating temperature from -40°C to 125°C
The TPS537G4S family of step-down controllers are high-performance, dual output multiphase controllers. with 16 phases. The controller has a high degree of programmability with support for up to eight separate pin-selectable configurations. Advanced control features such as dual-edge D-CAP+™ (DDCAP+) architecture with native TLVR support and full PID loop provide fast transient response and good current sharing minimizes output capacitance requirements and saves system cost. Controllers are fully compatible with relevant TI smart power stages. The device also provides optional phase shedding for efficiency improvements at different loads. All programmable parameters can be reported and configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | TPS537G4S Dual-Channel DDCAP+, Step-Down, Multiphase Controller with PWMVID, AVSBus 1.4, and PMBus Interfaces データシート | PDF | HTML | 2026年 3月 11日 |
設計と開発
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| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| FCLGA (ZLF) | 56 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブ拠点
- アセンブリ拠点
推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。