The SN54SC8T373-SEP device is an
octal transparent D-type latch with 3-State outputs.
The input is designed with a reduced
threshold circuit to support up translation when the supply voltage is larger than the input
voltage. Additionally, the 5V tolerant input pins enable down translation when the input
voltage is larger than the supply voltage. The output level is always referenced to the
supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The SN54SC8T373-SEP device is an
octal transparent D-type latch with 3-State outputs.
The input is designed with a reduced
threshold circuit to support up translation when the supply voltage is larger than the input
voltage. Additionally, the 5V tolerant input pins enable down translation when the input
voltage is larger than the supply voltage. The output level is always referenced to the
supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.