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SN74AVCH8T245

ACTIVE

8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

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Data sheet

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SN74AXCH8T245 ACTIVE 8-Bit Dual-Supply Bus Transceiver Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVCH8T245

ACTIVE
Data sheet Order now

Product details

Technology family AVC Bits (#) 8 High input voltage (min) (V) 1.2 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Bits (#) 8 High input voltage (min) (V) 1.2 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 TVSOP (DGV) 24 32 mm² 5 x 6.4 VQFN (RHL) 24 19.25 mm² 5.5 x 3.5
  • Control inputs (DIR and OE) VIH and VIL levels are referenced to VCCA voltage
  • Bus hold on data inputs eliminates the need for external pullup or pulldown resistors
  • VCC isolation feature
  • Fully configurable dual-rail design
  • I/Os are 4.6-V tolerant
  • Ioff supports partial-power-down mode operation
  • Maximum data rates:
    • 320Mbps (VCCA ≥ 1.8V and VCCB ≥ 1.8V)
    • 170Mbps (VCCA ≤ 1.8V or VCCB ≤ 1.8V)
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control inputs (DIR and OE) VIH and VIL levels are referenced to VCCA voltage
  • Bus hold on data inputs eliminates the need for external pullup or pulldown resistors
  • VCC isolation feature
  • Fully configurable dual-rail design
  • I/Os are 4.6-V tolerant
  • Ioff supports partial-power-down mode operation
  • Maximum data rates:
    • 320Mbps (VCCA ≥ 1.8V and VCCB ≥ 1.8V)
    • 170Mbps (VCCA ≤ 1.8V or VCCB ≤ 1.8V)
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74AVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The design of SN74AVCH8T245 references the control pins (DIR and OE) to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. It is not recommended to use pullup or pulldown resistors with the bus-hold circuitry.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature allows the outputs to be in the high-impedance state when either VCCA or VCCB is at GND. The bus-hold circuitry on the powered-up side always stays active.

The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

To put the device in the high-impedance state during power up or power down, OE must be tied to VCCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

The SN74AVCH8T245 is an 8-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

The design of SN74AVCH8T245 references the control pins (DIR and OE) to VCCA.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. It is not recommended to use pullup or pulldown resistors with the bus-hold circuitry.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device.

The VCC isolation feature allows the outputs to be in the high-impedance state when either VCCA or VCCB is at GND. The bus-hold circuitry on the powered-up side always stays active.

The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a ’245 function, with minimal printed circuit board redesign.

To put the device in the high-impedance state during power up or power down, OE must be tied to VCCA through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
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Technical documentation

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Type Title Date
* Data sheet SN74AVCH8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs datasheet (Rev. J) PDF | HTML 12 Apr 2024
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature LCD Module Interface Application Clip 09 May 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 Jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 Aug 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

User guide: PDF
Not available on TI.com
Simulation model

SN74AVCH8T245 IBIS Model

SCEM426.ZIP (68 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 24 Ultra Librarian
TVSOP (DGV) 24 Ultra Librarian
VQFN (RHL) 24 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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