Software
Firmware
TIDEP0033
SPI Master with Signal Path Delay Compensation Reference Design
TIDEP0033
Overview
The Programmable Real-time Unit within the Industrial Communication Subsystem (PRU-ICSS) enables you to support real-time critical applications without using FPGAs, CPLDs or ASICs.
This reference design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7 MHz.
Features
- SPI master protocol with adjustable signal path delay compensation (not requiring external hardware for signal path delay compensation)
- Up to 16.7-MHz SPI clock
- Supports ADS8688 SPI-communication protocol
- Automatic measurement of signal path delay for known secondary response
- This PRU-ICSS firmware has been validated with TIDA-00164 (ADS8688 and ISO7141CC) and contains firmware source code, implementation description and getting started instructions.
Industrial
- ATMs (Automated Teller Machines)
- Arm based computer on module
- Channel isolated analog input module
- Desktop POS
- Humanoid robot system controller
- Industrial robot analog I/O module
- Industrial robot digital I/O module
- Industrial robot mixed I/O module
- Merging Unit
- Mixed module (AI,AO,DI,DO)
- Single board computer
- Temperature input module
- Terminal Unit (RTU, DTU, FTU, TTU)
- Universal analog input module
- Voltage & current input module
- Weight module
- X86 based computer on module
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDUA38A.PDF (1141 K)
Reference design overview and verified performance test data
TIDRF78.PDF (248 K)
Detailed schematic diagram for design layout and components
TIDRF79.PDF (124 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRF80.ZIP (447 K)
Detailed overview of design layout for component placement
TIDRF82.ZIP (384 K)
Files used for 3D models or 2D drawings of IC components
TIDCAG2.ZIP (5563 K)
Design file that contains information on physical board layer of design PCB
TIDRF81.ZIP (447 K)
PCB layer plot file used for generating PCB design layout
Products
Includes TI products in the design and potential alternatives.
AND gates
SN74AUP2G08 — 2-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate
Data sheet: PDF | HTMLMulti-switch detection interface (MSDI) ICs
SN65HVS882 — 34-V, 8-channel digital-input serializer for industrial automation & process control
Data sheet: PDFStart development
Technical documentation
= Top documentation selected by TI
No results found. Please clear your search and try again.
View all 1
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | SPI Master With Signal Path Delay Compensation on PRU-ICSS Design Guide (Rev. A) | Jul. 13, 2015 |
Related design resources
Hardware development
EVALUATION BOARD
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.