Home
Design & development
Reference designs

TIDEP0033

SPI Master with Signal Path Delay Compensation Reference Design

Design files

TIDEP0033

Design files

Overview

The Programmable Real-time Unit within the Industrial Communication Subsystem (PRU-ICSS) enables you to support real-time critical applications without using FPGAs, CPLDs or ASICs.
This reference design describes the implementation of the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the 32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7 MHz.

Features
  • SPI master protocol with adjustable signal path delay compensation (not requiring external hardware for signal path delay compensation)
  • Up to 16.7-MHz SPI clock
  • Supports ADS8688 SPI-communication protocol
  • Automatic measurement of signal path delay for known secondary response
  • This PRU-ICSS firmware has been validated with TIDA-00164 (ADS8688 and ISO7141CC) and contains firmware source code, implementation description and getting started instructions.
Download View video with transcript Video

Design files & products

Design files

Download ready-to-use system files to speed your design process.

download Design guide — TIDEP0033
TIDUA38A.PDF (1142 KB)

Reference design overview and verified performance test data

download Assembly drawing — TIDEP0033
TIDRF80.ZIP (448 KB)

Detailed overview of design layout for component placement

download Bill of materials (BOM) — TIDEP0033
TIDRF79.PDF (124 KB)

Complete listing of design components, reference designators, and manufacturers/part numbers

download CAD/CAE symbol — TIDEP0033
TIDRF82.ZIP (384 KB)

Files used for 3D models or 2D drawings of IC components

download Gerber file — TIDEP0033
TIDCAG2.ZIP (5563 KB)

Design file that contains information on physical board layer of design PCB

download PCB layout — TIDEP0033
TIDRF81.ZIP (448 KB)

PCB layer plot file used for generating PCB design layout

download Schematic — TIDEP0033
TIDRF78.PDF (248 KB)

Detailed schematic diagram for design layout and components

Products

Includes TI products in the design and potential alternatives.

Linear & low-dropout (LDO) regulators

TPS717 — 150-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS766 —  250-mA ultra-low IQ low-dropout voltage regulator

Data sheet: PDF | HTML
Precision ADCs

ADS8688 — 16-bit, 500kSPS 8-channel single-supply SAR ADC with bipolar input ranges

Data sheet: PDF | HTML
Multi-switch detection interface (MSDI) ICs

SN65HVS882 — 34-V, 8-channel digital-input serializer for industrial automation & process control

Data sheet: PDF
Automotive LED drivers

TPIC2810 — 8-bit LED driver with I2C interface

Data sheet: PDF
AND gates

SN74AUP2G08 — 2-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate

Data sheet: PDF | HTML
AND gates

SN74LVC1G08 — 1-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

Data sheet: PDF | HTML
Isolated CAN transceivers

ISO1050 — Isolated 5-V CAN transceiver

Data sheet: PDF | HTML
Digital isolators

ISO7141CC — Quad-channel, 3/1, 50-Mbps digital isolator

Data sheet: PDF | HTML
Multi-channel ICs (PMICs)

TPS65910 — Integrated Power Management IC (PMIC) w/ 4 DC/DCs, 8 LDOs and RTC in 6x6mm QFN family

Data sheet: PDF | HTML
Multimedia & industrial networking SoCs

AM4379 — Sitara processor: Arm Cortex-A9, PRU-ICSS, EtherCAT, 3D graphics

Data sheet: PDF | HTML

Start development

Hardware development

Evaluation board

TMDSIDK437X — AM437x/AMIC120 Industrial Development Kit (IDK)

The Programmable Real-time Unit within the Industrial Communication Subsystem (PRU-ICSS) enables you to support real-time critical applications without using FPGAs, CPLDs or ASICs.
This reference design describes the implementation of the SPI master protocol with signal path delay compensation on (...)

EVM user’s guide: PDF
Supported products & hardware

Supported products & hardware

Hardware development
Reference design
TIDA-010016 — 8 Port IO-Link Master Reference Design TIDEP-0101 — Tamagawa Encoder Interface Protocol on AM437x Reference Design TIDEP0033 — SPI Master with Signal Path Delay Compensation Reference Design TIDEP0035 — ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design TIDEP0039 — Sercos III Slave For AM437x Communication Development Platform Reference Design TIDEP0057 — Multi-Protocol Digital Position Encoder Master Interface Reference Design With AM437x on PRU-ICSS TIDEP0064 — Real-time Ethernet Tracer with PRU-ICSS Reference Design TIDEP0065 — Enhanced I2C and SMbus Master Interface Reference Design with PRU-ICSS
In stock
Limit:
Out of stock on TI.com
Not available on TI.com

TMDSIDK437X — AM437x/AMIC120 Industrial Development Kit (IDK)

close
Latest version
Version: null
Release date:
open-in-new

View all versions

Hardware development
Reference design
TIDA-010016 — 8 Port IO-Link Master Reference Design TIDEP-0101 — Tamagawa Encoder Interface Protocol on AM437x Reference Design TIDEP0033 — SPI Master with Signal Path Delay Compensation Reference Design TIDEP0035 — ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design TIDEP0039 — Sercos III Slave For AM437x Communication Development Platform Reference Design TIDEP0057 — Multi-Protocol Digital Position Encoder Master Interface Reference Design With AM437x on PRU-ICSS TIDEP0064 — Real-time Ethernet Tracer with PRU-ICSS Reference Design TIDEP0065 — Enhanced I2C and SMbus Master Interface Reference Design with PRU-ICSS
TI’s Standard Terms and Conditions for Evaluation Items apply.

Software development

Firmware

TIDCAG3 — SPI Master With Signal Path Delay Compensation on PRU-ICSS Firmware

Supported products & hardware

Supported products & hardware

Hardware development
Reference design
TIDEP0033 — SPI Master with Signal Path Delay Compensation Reference Design
Download options

TIDCAG3 — SPI Master With Signal Path Delay Compensation on PRU-ICSS Firmware

close
Latest version
Version: 01.00.00.00
Release date: Jun 14, 2015
open-in-new

View all versions

download

SPI Master With Signal Path Delay Compensation on PRU-ICSS Firmware (zip)  — 28 K

SHA-256 checksum
Hardware development
Reference design
TIDEP0033 — SPI Master with Signal Path Delay Compensation Reference Design

Release Information

The design resource accessed as www.ti.com/lit/zip/tidcag3 or www.ti.com/lit/xx/tidcag3/tidcag3.zip has been migrated to a new user experience at www.ti.com/tool/download/TIDCAG3. Please update any bookmarks accordingly.

Technical documentation

star
= Top documentation selected by TI
No results found. Please clear your search and try again.
View all 1
Top documentation Type Title Format options Date
* Design guide SPI Master With Signal Path Delay Compensation on PRU-ICSS Design Guide (Rev. A) Jul 13, 2015

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support.

Disclaimer
See the important notice and disclaimer covering reference designs and other TI resources.