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TIDEP0057
Multi-Protocol Digital Position Encoder Master Interface Reference Design With AM437x on PRU-ICSS
TIDEP0057
Overview
This is a reference design for industrial communication on Sitara™ processors with programmable real-time unit and industrial communication subsystem (PRU-ICSS). This design describes the integrated multi-protocol digital position encoder master interface support. The supported digital position encoder master protocols are EnDat 2.2, HIPERFACE DSL ® and BiSS C. The integrated multi-protocol encoder master has the benefit to work without additional field programmable gate array (FPGA), application-specific integrated circuit (ASIC) and programmable logic device (PLD) while supporting multiple encoder protocols to save cost and reduce board space. This reference design utilizes the single chip drive evaluation board (TMDSIDK437X ) and universal digital interface to absolute position encoders reference design (TIDA-00179).
Features
- Multi-protocol digital position encoder master interface
- Supports EnDat 2.2, HIPERFACE DSL and BiSS C digital position encoder interfaces
- For integrated single chip drives, servo drives and remote position encoder master devices
- Digital position encoder master interface is supported by the PRU-ICSS peripheral within the Sitara AM437x processor
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDUB77.PDF (1357 K)
Reference design overview and verified performance test data
TIDRKN1.PDF (230 K)
Detailed schematic diagram for design layout and components
TIDRKN2.PDF (79 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRKN3.ZIP (54 K)
Detailed overview of design layout for component placement
TIDRKN6.ZIP (666 K)
Files used for 3D models or 2D drawings of IC components
TIDCBV8.ZIP (473 K)
Design file that contains information on physical board layer of design PCB
TIDRKN4.ZIP (217 K)
PCB layer plot file used for generating PCB design layout
TIDRKN5.ZIP (3301 K)
PCB layer plot file used for generating PCB design layout
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Technical documentation
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Multi-Protocol Position Encoder Interface With AM437x on PRU-ICSS Design Guide | Feb. 22, 2016 | |
| Technical article | Rise of the industrial robots. Overcoming the challenges of safe robot-human-inter | PDF | HTML | Nov. 08, 2016 | |
| White paper | Making factories smarter, more productive through predictive maintenance | Nov. 02, 2016 | ||
| Technical article | How to integrate position encoder master protocols into Sitara™ processor applicat | PDF | HTML | Aug. 25, 2016 |
Related design resources
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Reference designs
REFERENCE DESIGN
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