TIDEP0035
ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035
Overview
This reference design implements HIPERFACE DSL master protocol on Industrial Communication Sub-System (PRU-ICSS). The two-wire interface allows integration of position feedback wires into motor cable. It consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
Features
- HIPERFACE DSL master protocol with register compatible interface to existing FPGA IP core
- Programmable approach using ICSS_L concurrently with DS filter and Industrial Ethernet (single chip drive)
- Internal and external sync pulse sources
- Supports cable length of up to 100 meters
- Line-delay compensation
- 8x oversampling with sample-edge detection
- Line diagnostics – quality monitor
Design files & products
Design files
Download ready-to-use system files to speed your design process.
Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Products
Includes TI products in the design and potential alternatives.
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Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Design guide | ARM MPU With Integrated HIPERFACE DSL Master Interface Design Guide (Rev. B) | Oct. 07, 2016 | |
Application note | Part 1: Introduction to Industrial Communications | Dec. 01, 2015 | ||
Technical article | Designing an EMC-compliant interface to motor position encoders – Part 6 | PDF | HTML | Nov. 20, 2015 |
Related design resources
Reference designs
REFERENCE DESIGN
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