主页 逻辑和电压转换 触发器、锁存器和寄存器 D 型触发器
主页
逻辑和电压转换
触发器、锁存器和寄存器
D 型触发器

CD74FCT374

正在供货

具有三态输出的 BiCMOS FCT 接口逻辑八路 D 类触发器

立即订购
数据表

CD74FCT374

正在供货
数据表 立即订购

产品详情

Number of channels 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 80 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Number of channels 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -15 Supply current (max) (µA) 80 Features Very high speed (tpd 5-10ns) Operating temperature range (°C) 0 to 70 Rating Catalog
SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • BiCMOS Technology With Low Quiescent Power
  • 3-State Outputs Drive Bus Lines Directly
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 48-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP
  • BiCMOS Technology With Low Quiescent Power
  • 3-State Outputs Drive Bus Lines Directly
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 48-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP

The CD74FCT374 is an octal, edge-triggered, D-type flip-flop that uses a small-geometry BiCMOS technology and features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The eight flip-flops enter data into their registers on the low-to-high transition of the clock (CLK). The output-enable (OE\) input controls the 3-state outputs and is independent of the register operation. When OE\ is high, the outputs are in the high-impedance state.

A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT374 is characterized for operation from 0°C to 70°C.

The CD74FCT374 is an octal, edge-triggered, D-type flip-flop that uses a small-geometry BiCMOS technology and features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.

The eight flip-flops enter data into their registers on the low-to-high transition of the clock (CLK). The output-enable (OE\) input controls the 3-state outputs and is independent of the register operation. When OE\ is high, the outputs are in the high-impedance state.

A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT374 is characterized for operation from 0°C to 70°C.

filter 查找其他 D 型触发器
下载

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相同，且具有相同引脚
SN74AHCT374 正在供货 具有三态输出的八路 D 类边沿触发器 Larger voltage range (2V to 5.5V)

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 1
类型 标题 下载最新的英语版本 日期
* 数据表 BiCMOS Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs 数据表 2000年 7月 3日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训