The TPS51488 provides a complete power design for LPDDR5 memory systems with the lowest total cost and design size. The device meets the JEDEC standard for LPDDR5 power-up and power-down sequence requirement. The TPS51488 integrates two synchronous buck converters (VDD1 and VDD2) and a 1.5A LDO (VDDQ).
The TPS51488 employs D-CAP3 control mode with 600kHz switching frequency for fast transient response, good load/line regulation, and support for ceramic output capacitors with no external compensation circuit.
The TPS51488 is highly configurable and has high efficiency due to the integrated low Rdson power MOSFETs. The device supports flexible power state control, placing VDDQ at high-Z in S3 and discharging VDD1, VDD2, and VDDQ in S4/S5 state. Full protection features include OVP, UVP, OCP, UVLO, and thermal shutdown protection. The device is available in a thermally enhanced 18-pin HotRod VQFN package, and the junction temperature is specified from –40°C to 125°C.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | TPS51488 Complete LPDDR5 Memory Power Design datasheet (Rev. A) | PDF | HTML | 19 May 2026 |
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