The AFE79xx is a family of high performance, wide bandwidth multi-channel transceivers, integrating four RF sampling transmitter chains, four RF sampling receiver chains, and up to two RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows the device to generate and receive 3G, 4G, and 5G signals from wireless base stations, while the wide bandwidth capability of the AFE79xx devices is designed for multi-band 4G and 5G base stations.
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. The single or dual digital down converters (DDC) provide up to 600 MHz of combined signal BW. In TDD mode, the receiver channel can be configured to dynamically switch between the traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of re-using the same analog input for both purposes.
Each transmitter chain includes a single or dual digital up converters (DUCs) supporting up to 1200-MHz combined signal bandwidth. The output of the DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd or 3rd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1-dB analog and 0.125-dB digital steps.
The feedback path includes an 25-dB range DSA driving a 3-GSPS RF sampling ADC, followed by a DDC with up to 1200-MHz bandwidth.
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AFE7920 评估模块 (EVM) 是一个射频采样收发器平台，通过配置可同时支持最多四个发射、四个接收和两个反馈 (4T4R+2FB) 通道。
此电路板可评估 AFE7920 器件，这是一款四通道射频采样模拟前端 (AFE)，具有 14 位 12GSPS 数模转换器 (DAC)、14 位 3GSPS 模数转换器 (ADC) 以及为 DAC 和 ADC 生成高频时钟的片上集成锁相环 (PLL) 和压控振荡器 (VCO)。
AFE7920EVM 可在每个通道使用双频带数字升压转换器和降压转换器，从而同时将具有高动态范围的多个宽带信号合成并实现数字化。接收通道支持片上集成数字步进衰减器 (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
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