CSD75208W1015

ACTIVE

-20-V, P channel NexFET™ power MOSFET, dual Common Source WLP 1 mm x 1.5 mm, 108 mOhm, gate ESD prot

CSD75208W1015

ACTIVE

Product details

VDS (V) -20 VGS (V) -6 Type P-channel Configuration Dual Common Source Rds(on) at VGS=4.5 V (max) (mΩ) 108 Rds(on) at VGS=2.5 V (max) (mΩ) 150 VGSTH typ (typ) (V) -0.8 QG (typ) (nC) 1.9 QGD (typ) (nC) 0.23 QGS (typ) (nC) 0.48 ID - silicon limited at TC=25°C (A) 1.6 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
VDS (V) -20 VGS (V) -6 Type P-channel Configuration Dual Common Source Rds(on) at VGS=4.5 V (max) (mΩ) 108 Rds(on) at VGS=2.5 V (max) (mΩ) 150 VGSTH typ (typ) (V) -0.8 QG (typ) (nC) 1.9 QGD (typ) (nC) 0.23 QGS (typ) (nC) 0.48 ID - silicon limited at TC=25°C (A) 1.6 Logic level Yes Rating Catalog Operating temperature range (°C) -55 to 150
DSBGA (YZC) 6 2.1875 mm² 1.75 x 1.25
  • Dual P-Channel MOSFETs
  • Common Source Configuration
  • Small Footprint 1 mm × 1.5 mm
  • Gate-Source Voltage Clamp
  • Gate ESD Protection –3 kV
  • Pb Free
  • RoHS Compliant
  • Halogen Free
  • Dual P-Channel MOSFETs
  • Common Source Configuration
  • Small Footprint 1 mm × 1.5 mm
  • Gate-Source Voltage Clamp
  • Gate ESD Protection –3 kV
  • Pb Free
  • RoHS Compliant
  • Halogen Free

This device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications.

This device is designed to deliver the lowest on-resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications.

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Technical documentation

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Type Title Date
* Data sheet CSD75208W1015 Dual 20-V Common Source P-Channel NexFET Power MOSFET datasheet (Rev. A) PDF | HTML 16 May 2017
Application note MOSFET Support and Training Tools (Rev. F) PDF | HTML 14 Jun 2024
Application note Semiconductor and IC Package Thermal Metrics (Rev. D) PDF | HTML 25 Mar 2024
Application note Using MOSFET Transient Thermal Impedance Curves In Your Design PDF | HTML 18 Dec 2023
Application note Solving Assembly Issues with Chip Scale Power MOSFETs PDF | HTML 14 Dec 2023
Application note Using MOSFET Safe Operating Area Curves in Your Design PDF | HTML 13 Mar 2023
Application brief Tips for Successfully Paralleling Power MOSFETs PDF | HTML 31 May 2022
More literature WCSP Handling Guide 07 Nov 2019
Application note AN-1112 DSBGA Wafer Level Chip Scale Package (Rev. AI) 14 Jun 2019

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

CSD75208W1015 Unencrypted PSpice Model (Rev. A)

SLPM131A.ZIP (2 KB) - PSpice Model
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Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
DSBGA (YZC) 6 Ultra Librarian

Ordering & quality

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