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TPS51206

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2A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference for DDR2/3/3L/4

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Data sheet

TPS51206

ACTIVE
Data sheet Order now

Product details

Vin (min) (V) 1 Vin (max) (V) 3.5 Vout (min) (V) 0.5 Vout (max) (V) 0.9 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 105 Iq (typ) (mA) 0.17 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 1 Vin (max) (V) 3.5 Vout (min) (V) 0.5 Vout (max) (V) 0.9 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 105 Iq (typ) (mA) 0.17 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
WSON (DSQ) 10 4 mm² 2 x 2
  • Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
  • VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 V to 0.9 V
    • 2-A Peak Sink and Source Current
    • Requires Only 10-µF MLCC Output Capacitor
    • ±20 mV Accuracy
  • VTTREF Buffered Reference
    • VDDQ/2 ± 1% Accuracy
    • 10-mA Sink and Source Current
  • Supports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 Inputs
  • Overtemperature Protection
  • 10-Pin, 2 mm × 2 mm SON (DSQ) Package
  • Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
  • VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 V to 0.9 V
    • 2-A Peak Sink and Source Current
    • Requires Only 10-µF MLCC Output Capacitor
    • ±20 mV Accuracy
  • VTTREF Buffered Reference
    • VDDQ/2 ± 1% Accuracy
    • 10-mA Sink and Source Current
  • Supports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 Inputs
  • Overtemperature Protection
  • 10-Pin, 2 mm × 2 mm SON (DSQ) Package

The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).

The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.

The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).

The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.

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Technical documentation

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Type Title Date
* Data sheet TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR4 datasheet (Rev. E) PDF | HTML 19 Jul 2018
Application note Non-Isolated Point-of-Load Solutions for Tiger Lake in PC Applications (Rev. B) PDF | HTML 29 Apr 2021
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 09 Jul 2020
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
More literature Computing DDR DC-DC Power Solutions 22 Aug 2012
User guide TPS51206EVM-745 User's Guide 05 Aug 2011
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 28 Apr 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 20 Apr 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 31 Mar 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 26 Mar 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 26 Mar 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 26 Mar 2010

Design & development

Power-supply solutions

Explore solutions that include the TPS51206. TI offers power-supply solutions for TI and non-TI systems on a chip (SoCs), processors, microcontrollers, sensors, and field-programmable gate arrays (FPGAs).

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Evaluation board

TPS51206EVM-745 — 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference

The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low cost, low external component count systems where space is a key (...)

User guide: PDF
Not available on TI.com
Simulation model

TPS51206 PSpice Transient Model

SLUM198.ZIP (56 KB) - PSpice Model
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Simulation model

TPS51206 TINA-TI Transient Reference Design

SLUM249.TSC (142 KB) - TINA-TI Reference Design
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Simulation model

TPS51206 TINA-TI Transient Spice Model

SLUM248.ZIP (42 KB) - TINA-TI Spice Model
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Design guide: PDF
Schematic: PDF
Reference designs

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The PMP21065 Reference design operates off a typical 12V DC input to produce several common rails seen in set top boxes today. The key objectives of the design are to be low-cost, small in size and low stand-by power with high efficiency to help customers meet compliance to new regulatory (...)
Test report: PDF
Schematic: PDF
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WSON (DSQ) 10 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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